C8051F829-GS Silicon Laboratories Inc, C8051F829-GS Datasheet - Page 138

• Manufacturer Part Number: C8051F829-GS
• Description: IC MCU 8BIT 8KB FLASH 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F82xr

Specifications of C8051F829-GS

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1809-5

C8051F80x-83x
23. Port Input/Output
Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages) or 13 I/O pins
(16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one
of the internal digital resources as shown in Figure 23.4. Port pin P2.0 can be used as GPIO and is shared
with the C2 Interface Data signal (C2D). The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in
the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 23.5). The registers XBR0 and XBR1, defined in SFR Definition 23.1 and SFR Definition 23.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 23.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “7. Electrical Characteristics” on page 39.
138
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
CP0
PCA
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 23.1. Port I/O Functional Block Diagram
2
4
2
2
4
2
8
8
(ADC0, CP0, VREF, XTAL)
To Analog Peripherals
PnSKIP Registers
Rev. 1.0
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
To CS0
8
8
*Note: P1.4-P1.7
are not available
on the 16-pin
packages.
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
Cells
Cells
Cells
I/O
I/O
P1
I/O
P2
P0
External Interrupts
PnMDIN Registers
EX0 and EX1
PnMDOUT,
P0.0
P0.7
P1.0
P1.7*
P2.0