C8051F829-GS Silicon Laboratories Inc, C8051F829-GS Datasheet - Page 185

• Manufacturer Part Number: C8051F829-GS
• Description: IC MCU 8BIT 8KB FLASH 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F82xr

Specifications of C8051F829-GS

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1809-5

imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “26.3.4. SCL Low Timeout” on page 182). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 26.4).
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
EXTHOLD
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
0
1
Table 26.2. Minimum SDA Setup and Hold Times
Minimum SDA Setup Time
1 system clock + s/w delay
T
low
11 system clocks
– 4 system clocks
or
Rev. 1.0
*
Minimum SDA Hold Time
12 system clocks
3 system clocks
C8051F80x-83x
185