MCIMX515DJM8C Freescale Semiconductor, MCIMX515DJM8C Datasheet - Page 91

• Manufacturer Part Number: MCIMX515DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• Supply Voltage Range: 0.8V To 1.15V
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 80
Freescale Semiconductor
IP5
IP6
IP7
IP8
IP9
IP10
IP12
IP13
IP14
IP15
ID
Display interface clock period
Display pixel clock period
Screen width time
HSYNC width time
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
shows timing characteristics of signals presented in
Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level)
Parameter
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Symbol
Tdpcp
Thbi1
Thbi2
Tdicp
Tvbi1
Tvbi2
Thsw
Tvsw
Tsw
Tsh
DISP_CLK_PER_PIXEL
(SCREEN_HEIGHT -
BGXP - FW)
(SCREEN_HEIGHT)
(SCREEN_WIDTH -
(SCREEN_WIDTH)
BGYP - FH)
(HSYNC_WIDTH)
VSYNC_WIDTH
BGXP
BGYP
×
×
×
Value
Tdicp
Tdicp
(
Tsw
1
×
)
×
Tdicp
Tsw
×
×
Tdicp
Tsw
Figure 53
BGXP—Width of a horizontal blanking
Display interface clock.
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
before a first active data in a line. (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
active data in a line. (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
SCREEN_HEIGHT— screen height in lines
with blanking
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
Width a horizontal blanking after a last
and
Description
Figure
2
.
Electrical Characteristics
IPP_DISP_CLK
54.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
91