ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet
ATTINY4-TSHR
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ATTINY4-TSHR Summary of contents
Page 1
... Power-down Mode: • < 0.1µA at 1.8V Note: 1. The Analog to Digital Converter (ADC) is available in ATtiny5/10, only 2. At 5V, only ® 8-Bit Microcontroller 100 Years (1) 8-bit Microcontroller with 512/1024 Bytes In-System Programmable Flash ATtiny4/5/9/10 Preliminary Rev. 8127D–AVR–02/10 ...
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... As inputs, the port pins that are externally pulled low will source current if pull- up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 37. ...
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... Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. ...
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... The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 2.1 ...
Page 5
... PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. 8127D–AVR–02/10 ATtiny4/5/9/10 5 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATtiny4/5/9/10 6 Block Diagram of the AVR Architecture ...
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... The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8127D–AVR–02/10 for a detailed description. ATtiny4/5/9/10 “Instruction Set Sum- “Instruction Set Summary” on page 7 ...
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... R27 R28 R29 R30 R31 A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16 registers. For reasons of compatibility the registers are num- bered R16...R31, not R0...R15. 0 X-register Low Byte X-register High Byte Y-register Low Byte ...
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... This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. 8127D–AVR–02/10 The X-, Y-, and Z-registers R27 R29 R31 for details). , directly generated from the selected clock source for the CPU ATtiny4/5/9/ R26 R28 R30 “Instruction Set Sum ...
Page 10
... RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled ATtiny4/5/9/10 10 The Parallel Instruction Fetches and Instruction Executions T1 ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8127D–AVR–02/10 ; set Global Interrupt Enable ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) See “Code Examples” on page 5. ATtiny4/5/9/10 11 ...
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... The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the document “AVR Instruction Set” and ATtiny4/5/9/ ...
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... Set Summary” on page 152 “Instruction Set Summary” on page 152 “Instruction Set Summary” on page 152 “Instruction Set Summary” on page 152 ATtiny4/5/9/10 “Instruction Set Summary” “Instruction Set Summary” on for detailed for detailed for detailed information. ...
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... Since all AVR instructions are bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10 Program Counter (PC bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. ...
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... On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ATtiny4/5/9/10 0x0000 ... 0x003F 0x0040 ... 0x005F 0x0060 ... 0x3EFF 0x3F00 ... 0x3F01 0x3F02 ... 0x3F3F 0x3F40 ... 0x3F41 0x3F42 ... 0x3F7F 0x3F80 ... 0x3F81 0x3F82 ... 0x3FBF 0x3FC0 ... 0x3FC3 0x3FC4 ... 0x3FFF 0x4000 ... 0x41FF/0x43FF 0x4400 ...
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... I/O Memory The I/O space definition of the ATtiny4/5/9/10 is shown in All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general pur- pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin- gle bits can be checked by using the SBIS and SBIC instructions. See document “ ...
Page 17
... The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usu- ally active simultaneously with the CPU clock. 8127D–AVR–02/10 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the “Power Management and Sleep Modes” on page Clock Distribution ...
Page 18
... When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior required to ensure that the MCU is kept in reset during such changes in the clock frequency. ATtiny4/5/9/10 18 page 18) ...
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... T2 is the period corresponding to the new prescaler setting. 8127D–AVR–02/10 21. When switching between any clock sources, the clock system ensures “CLKPSR – Clock Prescale Register” on page ATtiny4/5/9/10 “CLKMSR – Clock Main Settings 22. The sys- 19 ...
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... Starting from Idle / ADC Noise Reduction / Standby Mode When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already run- ning and no oscillator start-up time is introduced. The ADC is available in ATtiny5/10, only. ATtiny4/5/9/10 20 Table 6-1 Table 6-1. Start-up Times when Using the Internal Calibrated Oscillator ...
Page 21
... External clock 1 1 Reserved CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R – CAL[7:0]: Oscillator Calibration Value Table 16-2, “Calibration Accuracy of Internal RC Oscillator,” on page 119. Calibration outside the range given is not guaranteed. ATtiny4/5/9/ – – CLKMS1 CLKMS0 R R R/W R Table 6- CAL3 ...
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... At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor the selected clock source has a frequency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To make sure the write procedure is not inter- rupted, interrupts must be disabled when changing prescaler settings. ATtiny4/5/9/ ...
Page 23
... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 17 ATtiny4/5/9/10. The figure is helpful in selecting an appropriate sleep mode. the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...
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... All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. ATtiny4/5/9/10 24 82. This will reduce power consumption in idle mode. If the “ ...
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... Digital – – – – ATtiny4/5/9/10 “Analog Comparator” on “Analog to Digital Converter” on page 84 for details on how to configure the Watchdog Timer. for details on which pins are enabled. If the input for details SM2 SM1 SM0 SE R/W R/W R/W R/W ...
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... The analog comparator cannot use the ADC input MUX when the ADC is shut down. The ADC is available in ATtiny5/10, only. • Bit 0 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. ATtiny4/5/9/10 26 Sleep Mode Select SM1 SM0 ...
Page 27
... Reset Sources The ATtiny4/5/9/10 have three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • ...
Page 28
... INTERNAL RESET 8.2.2 V Level Monitoring CC ATtiny4/5/9/10 have pin against fixed trigger levels. The trigger levels are set with VLM2:0 bits, see CC VCC Level Monitoring Control and Status register” on page The VLM circuit provides a status flag, VLMF, that indicates if voltage on the V selected trigger level ...
Page 29
... CC is below the reset level. See CC and Figure 8-3 on page 28. External Reset During Operation CC ATtiny4/5/9/10 Figure 17-48 on page “VCC Level Monitor” on page Table 8-4 on page 35 “System and Reset Characteristics” on page TOUT 147. 120. drops below ...
Page 30
... Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny4/5/9/10 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Figure 8-6 ...
Page 31
... Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant 8127D–AVR–02/10 WDT Configuration as a Function of the Fuse Settings of WDTON Safety WDT How to Level Initial State Disable the WDT Protected change 1 Disabled sequence 2 Enabled Always enabled ATtiny4/5/9/10 Table 8-1 on page 31. for details. How to Change Time-out No limitations Protected change sequence 31 ...
Page 32
... Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the ATtiny4/5/9/10 32 r16, RSTFLR r16, ~(1< ...
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... Interrupt Mode 1 0 System Reset Mode Interrupt and System 1 1 Reset Mode x x System Reset Mode 1. WDTON configuration bit set to “0“ means programmed and “1“ means unprogrammed. ATtiny4/5/9/10 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 33 ...
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... When this bit is set the VLM interrupt is enabled. A VLM interrupt is generated every time the VLMF flag is set. • Bits 5:3 – Res: Reserved Bits These bits are reserved. For ensuring compatibility with future devices, these bits must be writ- ten to zero, when the register is written. ATtiny4/5/9/10 34 34. Watchdog Timer Prescale Select WDP2 ...
Page 35
... Initial Value • Bits 7:4, 2– Res: Reserved Bits These bits are reserved bits in ATtiny4/5/9/10 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
Page 36
... In case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations. The most typical and general setup for interrupt vector addresses in ATtiny4/5/9/10 is shown in the program example below. Address Labels Code ...
Page 37
... SPH,r16 ldi r16, low(RAMEND top of RAM out SPL,r16 sei <instr> ... “EICRA – External Interrupt Control Register A” on page “Clock System” on page ATtiny4/5/9/10 ; Set Stack Pointer ; Enable interrupts 38. When the INT0 interrupt is 17. “Clock System” on page Figure 9-1. 17. 37 ...
Page 38
... The level and edges on the external INT0 pin that activate the interrupt are defined in If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is ATtiny4/5/9/10 38 Timing of pin change interrupts pin_lat ...
Page 39
... The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request – – – – – – – – ATtiny4/5/9/ – – – INTO R – – – INTF0 R EIMSK EIFR 39 ...
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... Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny4/5/9/ ...
Page 41
... Ground as indicated in Figure 10-1 on page for a complete list of parameters. Pxn C pin “Register Description” on page 46. Refer to the individual module sections for a full description of the alter- ATtiny4/5/9/10 41. See “Electrical Characteristics” Logic See Figure "General Digital I/O" for Details 51. “ ...
Page 42
... Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description” on page PORTxn bits at the PORTx I/O address, the PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address. ATtiny4/5/9/10 42 (1) SLEEP ...
Page 43
... Output Output Yes “PORTCR – Port Control Register” on page ATtiny4/5/9/10 Comment Tri-state (hi-Z) Sources current if pulled low externally Output low (sink) NOT RECOMMENDED. Output low (sink) and internal pull-up active. Sources current through the internal pull-up resistor and consumes power constantly ...
Page 44
... It is clocked into the PINxn Register at the succeeding positive clock edge. As indi- cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. ATtiny4/5/9/10 44 r16 ...
Page 45
... PORTx, r16 PINxn r17 Figure 10-2 on page 42, the digital input signal can be clamped to ground at the “Alternate Port Functions” on page or GND is not recommended, since this may cause excessive currents if the pin is CC ATtiny4/5/9/10 0xFF nop in r17, PINx 0x00 ...
Page 46
... Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In below is shown how the port pin control signals from the simplified be overridden by alternate functions. ATtiny4/5/9/10 46 r16,(1<<PUEB2) r17,(1<<PB0) r18,(1<<DDB1)|(1<<DDB0) ...
Page 47
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clk , and SLEEP are common to all ports. All other signals are unique for each pin. I/O ATtiny4/5/9/10 REx Q D PUExn ...
Page 48
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny4/5/9/10 48 summarizes the function of the overriding signals. The pin and port Figure 10-6 on page 47 are not shown in the succeeding tables ...
Page 49
... ADC Input Channel 2 CLKO: System Clock Output PB2 INT0: External Interrupt 0 Source PCINT2: Pin Change Interrupt 0, Source 2 T0: Timer/Counter0 Clock Source ADC3: ADC Input Channel 3 PB3 PCINT3: Pin Change Interrupt 0, Source 3 RESET: Reset Pin ATtiny4/5/9/10 Table 10-3 on page 49. (ATtiny5/10, only) (ATtiny5/10, only) 49 ...
Page 50
... Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Notes: ATtiny4/5/9/10 50 and Table 10-5 on page 51 relate the alternate functions of Port B to the overriding Figure 10-6 on page 47. Overriding Signals for Alternate Functions in PB3..PB2 PB3/ADC3/RESET/PCINT3 (1) RSTDISBL 1 (1) RSTDISBL 0 ...
Page 51
... EXT_CLOCK is 1 when external clock is selected as main clock – – – “Break-Before-Make Switching” on page – – – ATtiny4/5/9/10 PB0/ADC0/AIN0/OC0A/PCINT0 OC0A Enable OC0A 0 (PCINT0 • PCIE0) + ADC0D PCINT0 • PCIE0 PCINT0 Input ADC0/Analog Comparator Positive Input – – – BBMB R/W 0 ...
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... PORTB – Port B Data Register Bit 0x02 Read/Write Initial Value 10.4.4 DDRB – Port B Data Direction Register Bit 0x01 Read/Write Initial Value 10.4.5 PINB – Port B Input Pins Bit 0x00 Read/Write Initial Value ATtiny4/5/9/ – – – – – – ...
Page 53
... Count Clear Control Logic Direction TOP BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Values = OCRnB ICFn (Int.Req.) ICRn TCCRnA TCCRnB ATtiny4/5/9/10 TOVn (Int.Req.) Clock Select clk Tn Edge Detector ( From Prescaler ) = 0 OCnA (Int.Req.) Waveform Generation OCnB (Int.Req.) Waveform Generation ( From Analog Comparator Ouput ) ...
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... Constant BOTTOM MAX TOP ATtiny4/5/9/10 54 “Pinout of ATtiny4/5/9/10” on page “Register Description” on page 60. The compare match event will also set the Compare Match 82). The Input Capture unit includes a digital filtering unit (Noise Definitions Description The counter reaches BOTTOM when it becomes 0x00 ...
Page 55
... The number of system 8127D–AVR–02/10 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O for an illustration of the prescaler unit. Clear Synchronization 1. The synchronization logic on the input pins ( for details. ATtiny4/5/9/10 clk T0 T0) is shown in Figure 11-3 on page /8, f /64, f /256 ...
Page 56
... An external clock source can not be prescaled. 11.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 11-4 on page 57 ATtiny4/5/9/10 56 pulse for each positive (CS2 negative (CS2 ...
Page 57
... Signalize that TCNT0 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATtiny4/5/9/10 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM “ ...
Page 58
... When the CPU reads the ICR0H I/O location it will access the TEMP Register. The ICR0 Register can only be written when using a Waveform Generation mode that utilizes the ICR0 Register for defining the counter’s TOP value. In these cases the Waveform Genera- ATtiny4/5/9/10 58 DATA BUS TEMP (8-bit) ...
Page 59
... Changing the edge sensing must be done as early as possible after the ICR0 Register has been read. After a change of the edge, the Input Capture Flag (ICF0) must be 8127D–AVR–02/10 72. ATtiny4/5/9/10 “Accessing 16-bit Registers” (Figure 11-3 on page 56). The edge detector is also ...
Page 60
... Output Compare unit are gray shaded. Figure 11-6. Output Compare Unit, Block Diagram The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the ATtiny4/5/9/10 60 (“Modes of Operation” on page 63). ...
Page 61
... Normal mode. The OC0x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 8127D–AVR–02/10 72. ATtiny4/5/9/10 “Accessing 16-bit Registers” 61 ...
Page 62
... The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See The COM0x1:0 bits have no effect on the Input Capture unit. ATtiny4/5/9/10 62 Waveform D ...
Page 63
... The OCR0A or ICR0 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. 8127D–AVR–02/10 Table 11-2 on page 75. For fast PWM mode refer to 62) “Timer/Counter Timing Diagrams” on page ATtiny4/5/9/10 Table 11-3 on Table 11-4 on 70. 63 ...
Page 64
... The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope ATtiny4/5/9/ ...
Page 65
... Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR0x Registers are written. 8127D–AVR–02/10 log R = ---------------------------------- - FPWM ATtiny4/5/9/ TOP log Figure 11-9 on page OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) ...
Page 66
... TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope ATtiny4/5/9/10 66 Table 11-3 on page f ...
Page 67
... Compare Registers. If the TOP value is lower than any of the 8127D–AVR–02/ log TOP + ---------------------------------- - PCPWM log ATtiny4/5/9/10 Figure 11-10 on page OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 ...
Page 68
... OCR0x Register is updated by the OCR0x Buffer Register, (see 10 on page 67 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and ATtiny4/5/9/ ...
Page 69
... TOP R = ---------------------------------- - PFCPWM log Figure 11-11 on page shows the output generated is, in contrast to the phase correct ATtiny4/5/9/ 69. The figure shows phase and fre- OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 70
... OCR0x Register is updated with the OCR0x buffer value (only for modes utilizing double buffering). ting of OCF0x. Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx OCFnx ATtiny4/5/9/ clk_I ---------------------------- - OCnxPFCPWM ⋅ TOP Figure 11-12 on page 70 OCRnx - 1 OCRnx OCRnx Value Table 11-4 on ⋅ ...
Page 71
... TOP in various modes. When clk I/O clk Tn /1) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value shows the same timing data, but with the prescaler enabled. ATtiny4/5/9/10 OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 ...
Page 72
... The following code example shows how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B and ICR0 Registers. ATtiny4/5/9/10 72 I/O Tn /8) ...
Page 73
... TCNT0H,r17 out TCNT0L,r16 ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ... See “Code Examples” on page 5. ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ; Restore global interrupt flag out SREG,r18 ret See “Code Examples” on page 5. ATtiny4/5/9/10 73 ...
Page 74
... OC0B output overrides the normal port functionality of the I/O pin it is connected to. Note, however, that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver. ATtiny4/5/9/10 74 See “Code Examples” on page 5 ...
Page 75
... Counting up: Clear OC0A/OC0B on compare match 0 Counting down: Set OC0A/OC0B on compare match (1) Counting up: Set OC0A/OC0B on compare match 1 Counting down: Clear OC0A/OC0B on compare match 1. A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. “Phase Correct PWM Mode” on page 66 ATtiny4/5/9/10 for more details. “Fast PWM 75 ...
Page 76
... This bit selects which edge on the Input Capture pin (ICP0) that is used to trigger a capture event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. ATtiny4/5/9/10 76 (“Modes of Operation” on page ...
Page 77
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge 1 1 External clock source on T0 pin. Clock on rising edge FOC0A FOC0B – ATtiny4/5/9/10 74 – – – – Figure 11- 0 – TCCR0C ...
Page 78
... A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an ATtiny4/5/9/ ...
Page 79
... Registers” on page R/W R/W R/W R “Accessing 16-bit Registers” on page – – ICIE0 “Interrupts” on page “Interrupts” on page 36) is executed when the TOV0 flag, located in TIFR0, is set. ATtiny4/5/9/10 72 ICR0[15:8] ICR0[7:0] R/W R – – OCIE0B OCIE0A R R R/W ...
Page 80
... Bit 0x2F Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. ATtiny4/5/9/ – ...
Page 81
... When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 8127D–AVR–02/10 ATtiny4/5/9/10 81 ...
Page 82
... This bit is reserved and will always read zero. • Bit 5 – ACO: Analog Comparator Output Enables output of analog comparator. The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay clock cycles. ATtiny4/5/9/10 82 12-1. for pin use of analog comparator, and for alternate pin usage ...
Page 83
... Table 12-1. Selecting Source for Analog Comparator Interrupt. ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle. 1 Reserved 0 Comparator Interrupt on Falling Output Edge. 1 Comparator Interrupt on Rising Output Edge – – – – ATtiny4/5/9/ – – ADC1D ADC0D DIDR0 R R R/W R ...
Page 84
... The ADC contains a Sample-and-Hold-circuit, which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in on page Internal reference voltage of V The ADC is not available in ATtiny4/9. 13.3 Operation In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction Register must be disabled. This is done by clearing the PRADC bit. See tion Register” ...
Page 85
... ADCSRB ADMUX TRIGGER DECODER SELECT VREF 8-BIT DAC INPUT MUX “PRR – Power Reduction Register” on page Table 13-4 on page 96 ATtiny4/5/9/10 ADCSRA PRESCALER CONVERSION LOGIC - + SAMPLE & HOLD COMPARATOR for a list of the trigger sources. When a positive edge ADCL ADC IRQ 26). ...
Page 86
... Figure 13-3. ADC Prescaler The ADC module contains a prescaler, as illustrated in an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is ATtiny4/5/9/10 86 ADTS[2:0] ADIF SOURCE 1 ...
Page 87
... ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. 8127D–AVR–02/ MUX Sample & Hold Update MUX Sample & Hold Update ATtiny4/5/9/10 Table 13-1 on page Figure 13-4. First Conversion Conversion Complete Figure One Conversion ...
Page 88
... ADIF ADCL In Free Running mode (see conversion completes, while ADSC remains high. Figure 13-7. ADC Timing Diagram, Free Running Conversion For a summary of conversion times, see Table 13-1. Condition First conversion Normal conversions Auto Triggered conversions ATtiny4/5/9/ Prescaler MUX Sample & Reset ...
Page 89
... CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 8127D–AVR–02/10 ) and Channels that exceed V GND REF cc ATtiny4/5/9/10 will result in codes saturated at 0xFF. REF 89 ...
Page 90
... S/H capacitor. Signal components higher than the Nyquist frequency (f distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. ATtiny4/5/9/ ADCn ...
Page 91
... LSB). Ideal value: 0 LSB. Figure 13-9. Offset Error Output Code 8127D–AVR–02/10 and GND pins as possible. CC Section 13.7 on page 89. A good system design with properly placed, external Offset Error ATtiny4/5/9/ steps REF n -1. Ideal ADC Actual ADC V Input Voltage ...
Page 92
... Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 13-11. Integral Non-linearity (INL) Output Code ATtiny4/5/9/10 92 Gain Error Ideal ADC ...
Page 93
... LSB. 8127D–AVR–02/10 Output Code 0xFF 1 LSB 0x00 0 ADCL (see Table 13-2 on page 94) is the voltage on the selected input pin and V IN ATtiny4/5/9/10 V Input Voltage REF ⋅ V 256 IN = ---------------------- - the ...
Page 94
... Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con- version on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. ATtiny4/5/9/ ...
Page 95
... Interrupt Flag. Note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the 8127D–AVR–02/10 ADC Prescaler Selections ADPS1 – – – – ATtiny4/5/9/10 ADPS0 Division Factor 128 – ADTS2 ADTS1 ADTS0 R R/W R/W R ADCSRB 95 ...
Page 96
... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATtiny4/5/9/10 96 ADC Auto Trigger Source Selections ...
Page 97
... Programming” on page 14-1. TINY PROGRAMMING INTERFACE (TPI) RESET PHYSICAL TPICLK LAYER TPIDATA ATtiny4/5/9/10 108. NVM CONTROLLER ACCESS LAYER NON-VOLATILE MEMORIES DATA BUS 97 ...
Page 98
... RESET pin. The RESET pin must be kept at 12V for the entire programming session (see Table 16-4 on page 120) RST t RST +5V ATtiny4/5/9/10 TPIDATA/PB0 PB3/RESET GND V CC TPICLK/PB1 PB2 Figure 14-3 120) and then set the RESET pin low. ...
Page 99
... Stop bit 1 (always high) Stop bit 2 (always high) ⊗ ⊗ ⊗ ⊗ ⊗ ⊗ Parity bit using even parity Data bits of the character DATA CHARACTER IDLE BREAK CHARACTER IDLE ATtiny4/5/9/ longer applied to the SP1 ⊗ ⊗ SP1 SP2 107. SP2 IDLE/ST IDLE/ST IDLE/ST 99 ...
Page 100
... If a collision is detected during transmission, the output driver is disabled. The TPI access layer enters the error state and the TPI physical layer is put into receive mode, waiting for a BREAK character. ATtiny4/5/9/10 100 Figure 14-6. Data is changed at falling edges and sampled at rising edges. ...
Page 101
... The communication is based on message format, where each message comprises an instruction followed by one or more byte-sized operands. The instruction is always sent by the external programmer but operands are sent either by the external programmer or by the TPI access layer, depending on the type of instruction issued. 8127D–AVR–02/10 ATtiny4/5/9/10 101 ...
Page 102
... The access layer will stay in the error state until a BREAK character has been received, after which it is taken back to its default state consequence, the external programmer can always synchronize the proto- col by simply transmitting two successive BREAK characters. ATtiny4/5/9/10 102 page 103. ...
Page 103
... Serial STore to Control and Status space a, data using direct addressing Key, {8{data}} Serial KEY The Serial Load from Data Space (SLD) Instruction Opcode DS[PR] 0010 0000 DS[PR] 0010 0100 ATtiny4/5/9/10 14-1. Operation data data ← PR DS[PR] DS[PR] ← PR PR[a] ...
Page 104
... The SOUT instruction stores the data byte that is shifted into the physical layer shift register to the I/O space. The instruction uses direct addressing, the address consisting of the 6 address bits of the instruction, as shown in Table 14-6. Operation ← I/O[a] ATtiny4/5/9/10 104 The Serial Store to Data Space (SLD) Instruction Opcode ← data 0110 0000 ← ...
Page 105
... Opcode ← 1100 aaaa data The Serial KEY signaling (SKEY) Instruction Opcode 1110 0000 {8[data}} ATtiny4/5/9/10 Table Remarks Bits marked ‘a’ form the direct, 4-bit addres Table Remarks Bits marked ‘a’ form the direct, 4-bit addres Remarks Data bytes follow after instruction Table 14-10 ...
Page 106
... TPIPCR – Tiny Programming Interface Physical Layer Control Register Bit CSS: 0x02 Read/Write Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read zero. ATtiny4/5/9/10 106 Table Name Bit 7 Bit 6 Bit 5 TPIIR Tiny Programming Interface Identification Code Reserved – ...
Page 107
... NVM programming is disabled by writing this bit to zero. 8127D–AVR–02/10 Table 14-13 shows the available Guard Time settings. GT1 – – – – ATtiny4/5/9/10 GT0 Guard Time (Number of IDLE bits) 0 +128 (default value) 1 +64 0 + – – NVMEN – R TPIPCR 107 ...
Page 108
... Tiny Programming Interface (TPI). In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections which are read-only. NVM can be programmed at 5V, only. ATtiny4/5/9/10 108 Figure 14-2 on page 98. The external programmer can read and program the NVM ...
Page 109
... The ATtiny4/5/9/10 have the following, embedded NVM: • Non-Volatile Memory Lock Bits • Flash memory with four separate sections 15.3.1 Non-Volatile Memory Lock Bits The ATtiny4/5/9/10 provide two Lock Bits, as shown in Table 15-1. Lock Bit NVLB2 NVLB1 The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the addi- tional security shown in command, only ...
Page 110
... Flash Memory The embedded Flash memory of ATtiny4/5/9/10 has four separate sections, as shown in 15-3 and Table 15-3. Section Code (program memory) Configuration Signature Calibration Notes: Table 15-4. Section Code (program memory) Configuration Signature Calibration Notes: 15.3.3 Configuration Section ATtiny4/5/9/10 have one configuration byte, which resides in the configuration section. See Table 15-5 ...
Page 111
... Most of this memory section is reserved for internal use, as shown in Table 15-7. Signature word address 0x00 0x01 0x02 ... 0x0F ATtiny4/5/9/10 have a three-byte signature code, which can be used to identify the device. The three bytes reside in the signature section, as shown in ATtiny4/5/9/10 is given in Table 15-8. Part ATtiny4 ATtiny5 ...
Page 112
... Programming any part of the NVM will automatically inhibit the following operations: • All programming to any other part of the NVM • All reading from any NVM location ATtiny4/5/9/10 support only external programming. Internal programming operations to NVM have been disabled, which means any internal attempt to write or erase NVM locations will fail. 15.4.1 ...
Page 113
... Lock Bits. For security reasons, the NVM Lock Bits are not reset before the code section has been completely erased. Configuration, Signature and Calibration sections are not changed. 8127D–AVR–02/10 PADDRMSB PADDR FLASH SECTION PAGE ... PAGE ADDRESS WITHIN A FLASH ... SECTION ... ATtiny4/5/9/10 WADDRMSB+1 WADDRMSB 1 WADDR 0/1 FLASH PAGE 00 WORD ADDRESS 01 WITHIN A FLASH PAGE WORD ... ... ... ...
Page 114
... Write the low byte of the data to the low byte of a configuration word location 3. Write the high byte of the data to the high byte of the same configuration word location. This will start the Flash write operation. 4. Wait until the NVMBSY bit has been cleared ATtiny4/5/9/10 114 8127D–AVR–02/10 ...
Page 115
... NVM Lock Word location. 4. Wait until the NVMBSY bit has been cleared. 15.5 Self programming The ATtiny4/5/9/10 don't support internal programming. 15.6 External Programming The method for programming the Non-Volatile Memories by means of an external programmer is referred to as external programming. External programming can be done both in-system or in mass production ...
Page 116
... These bits are reserved and will always read zero. • Bit 5:0 - NVMCMD[5:0]: Non-Volatile Memory Command These bits define the programming commands for the flash, as shown in Table 15-10. NVM Programming commands Operation Type General Section Word ATtiny4/5/9/10 116 NVMBSY – – ...
Page 117
... CC - ATtiny4/5/9/10 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
Page 118
... Values are with external clock using methods described in enabled (PRR = 0xFF) and there is no I/O drive. 7. BOD Disabled. 16.3 Speed The maximum operating frequency of the device depends on V relationship between maximum frequency vs. V Figure 16-1. Maximum Frequency vs. V ATtiny4/5/9/10 118 = -40°C to +85°C (Continued) A Condition Min. Active 1MHz ...
Page 119
... Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). V IH1 V IL1 V = 1.8 - 5.5V CC Min. 0 250 100 100 ATtiny4/5/9/10 Figure 17-39 on page 143 and Accuracy at given Voltage Temperature & Temperature 25°C Fixed temp. within: -40°C – 85° 2 4 Max ...
Page 120
... V Level Monitor CC Table 16-6. Parameter Trigger level VLM1L Trigger level VLM1H Trigger level VLM2 Trigger level VLM3 Settling time VMLM2,VLM3 (VLM1H,VLM1L) Note: ATtiny4/5/9/10 120 Reset, VLM, and Internal Voltage Characteristics Parameter Condition RESET Pin Threshold Voltage V CC Minimum pulse width ...
Page 121
... REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 200 kHz Free Running Conversion 65 50 GND 0 ATtiny4/5/9/10 Min Typ Max Units < - 750 500 ns 100 CLK Typ Max Units 8 Bits 1.0 LSB 1.0 LSB 1 ...
Page 122
... IVCH TPICLK Table 16-9. Symbol 1/t CLCL t CLCL t CLCH t CHCH t IVCH t CHIX t CLOV ATtiny4/5/9/10 122 Receive Mode t CHIX t t CLCH CHCL t CLCL Serial Programming Characteristics, T wise Noted) Parameter Clock Frequency Clock Period Clock Low Pulse Width Clock High Pulse Width Data Input to Clock High Setup Time ...
Page 123
... Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock (see Figure 17-1 and Figure 2.3 % (1) 6 The ADC is available in ATtiny5/10, only ATtiny4/5/9/10 = average switching frequency of SW for details. Typical numbers 4MHz 8MHz ...
Page 124
... Active Supply Current Figure 17-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 17-2. Active Supply Current vs. frequency ( MHz) 4.5 3.5 2.5 1.5 0.5 ATtiny4/5/9/10 124 ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 0.2 ...
Page 125
... ACTIVE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 1 MHz 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 ATtiny4/5/9/10 (Internal Oscillator, 8 MHz INTERNAL OSCILLATOR, 8 MHz 3.5 4 4.5 V (V) CC (Internal Oscillator, 1 MHz 3 (V) CC -40 °C 25 °C 85 °C 5 5.5 -40 ° ...
Page 126
... Figure 17-5. Active Supply Current vs. V Figure 17-6. Active Supply Current vs. V 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 ATtiny4/5/9/10 126 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 128 KHz 0.12 0.1 0.08 0.06 0.04 0.02 0 1 ACTIVE SUPPLY CURRENT vs. V ...
Page 127
... Figure 17-8. Idle Supply Current vs. Frequency ( MHz) 0,8 0,6 0,4 0,2 8127D–AVR–02/10 IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0 0,1 0,2 0,3 0,4 IDLE SUPPLY CURRENT vs. FREQUENCY 1 1 ATtiny4/5/9/10 (PRR=0xFF) 0,5 0,6 0,7 0,8 Frequency (MHz) (PRR=0xFF) 3 Frequency (MHz) 5.5 V 5.0 V 4 ...
Page 128
... Figure 17-10. Idle Supply Current vs. V 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 ATtiny4/5/9/10 128 (Internal Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 2 2,5 3 3,5 V (V) CC (Internal Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz ...
Page 129
... POWER-DOWN SUPPLY CURRENT vs. V 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 POWER-DOWN SUPPLY CURRENT vs. V 1,5 2 2,5 3 ATtiny4/5/9/10 (Watchdog Timer Disabled WATCHDOG TIMER DISABLED 3.5 4 4.5 V (V) CC (Watchdog Timer Enabled WATCHDOG TIMER ENABLED 3,5 4 4 ° ...
Page 130
... Figure 17-13. I/O pin Pull-up Resistor Current vs. Input Voltage ( Figure 17-14. I/O Pin Pull-up Resistor Current vs. input Voltage ( ATtiny4/5/9/10 130 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 0,2 0,4 0,6 0,8 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 1.8V 1,2 1,4 1,6 1,8 ...
Page 131
... Figure 17-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( 8127D–AVR–02/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0 0,2 0,4 0,6 0,8 ATtiny4/5/9/ 1.8V 1,2 1,4 1,6 V (V) RESET 25 °C 85 °C -40 ° °C -40 ° ...
Page 132
... Figure 17-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( Figure 17-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 120 100 ATtiny4/5/9/10 132 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (V) RESET RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0,5 1 1,5 2 2,5 V (V) RESET = 2 ...
Page 133
... I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.5 1 1.5 2 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 ATtiny4/5/9/10 = 1.8V 1.8V CC 2.5 3 3.5 4 4.5 I (mA 3V (mA °C 25 °C -40 ° ° ...
Page 134
... Figure 17-21. I/O pin Output Voltage vs. Sink Current (V Figure 17-22. I/O Pin Output Voltage vs. Source Current (V ATtiny4/5/9/10 134 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1 0.8 0.6 0.4 0 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 ...
Page 135
... Figure 17-24. I/O Pin output Voltage vs. Source Current (V 5.2 4.8 4.6 4.4 4.2 8127D–AVR–02/10 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT ATtiny4/5/9/ (mA 5V (mA) OH -40 °C 25 °C 85 °C 10 -40 ° ...
Page 136
... Figure 17-25. Reset Pin as I/O, Output Voltage vs. Sink Current Figure 17-26. Reset Pin as I/O, Output Voltage vs. Source Current ATtiny4/5/9/10 136 OUTPUT VOLTAGE vs. SINK CURRENT 1 1.8 V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 OUTPUT VOLTAGE vs. SOURCE CURRENT 0.2 0.4 0.6 0.8 RESET PIN AS I/O 3 ...
Page 137
... Figure 17-28. I/O Pin Input threshold Voltage vs 2,5 2 1,5 1 0,5 0 8127D–AVR–02/10 I/O PIN INPUT THRESHOLD VOLTAGE vs. V 1,5 2 2,5 3 I/O PIN INPUT THRESHOLD VOLTAGE vs. V 1,5 2 2,5 3 ATtiny4/5/9/ Pin Read as ‘1’ VIH, IO PIN READ AS '1' 3 Pin Read as ‘0’ ...
Page 138
... Figure 17-30. Reset Pin as I/O, Input Threshold Voltage vs 2,5 2 1,5 1 0,5 0 1,5 ATtiny4/5/9/10 138 I/O PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C 2 2,5 3 RESET PIN AS I/O THRESHOLD VOLTAGE vs 2 3 (V) ...
Page 139
... RESET PIN AS I/O THRESHOLD VOLTAGE vs. V 1,5 2 2,5 3 RESET PIN AS I/O, INPUT HYSTERESIS vs. VCC -40 °C 25 °C 85 °C 1,5 2 2,5 3 ATtiny4/5/9/ I/O pin Read as ‘0’ VIL, RESET READ AS '0' 3,5 4 4,5 V (V) CC (Reset Pin Used as I/ PIN READ AS "0" ...
Page 140
... Figure 17-33. Reset Input Threshold Voltage vs. V 2,5 2 1,5 1 0,5 0 1,5 Figure 17-34. Reset Input Threshold Voltage vs. V 2,5 2 1,5 1 0,5 0 1,5 ATtiny4/5/9/10 140 RESET INPUT THRESHOLD VOLTAGE vs. V -40 °C 25 °C 85 °C 2 2,5 3 RESET INPUT THRESHOLD VOLTAGE vs 2 I/O Pin Read as ‘1’) CC ...
Page 141
... Figure 17-35. Reset Pin, Input Hysteresis vs 0,8 0,6 0,4 0,2 0 17.8 Analog Comparator Offset Figure 17-36. Analog Comparator Offset 8127D–AVR–02/10 RESET PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C 1,5 2 2,5 3 ANALOG COMPARATOR OFFSET 0.006 0.004 0.002 ATtiny4/5/9/ 3,5 4 4 5,5 - 141 ...
Page 142
... Internal Oscillator Speed Figure 17-37. Watchdog Oscillator Frequency vs. V Figure 17-38. Watchdog Oscillator Frequency vs. Temperature ATtiny4/5/9/10 142 WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 107 106 105 104 103 102 101 100 99 1.5 2 2.5 3 WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 110 ...
Page 143
... CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.4 8.2 8 7.8 7.6 7.4 1.5 2 2.5 3 CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 8.1 8 7.9 7.8 7.7 7.6 -40 - ATtiny4/5/9/10 CC 3 Temperature -40 °C 25 °C 85 °C 5.5 5.0 V 3.0 V 1.8 V 100 143 ...
Page 144
... Figure 17-41. Calibrated Oscillator Frequency vs, OSCCAL Value 17.10 VLM Thresholds Figure 17-42. VLM1L Threshold of V 1.42 1.41 1.4 1.39 1.38 1.37 1.36 1.35 1.34 ATtiny4/5/9/10 144 CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 128 144 160 176 192 208 224 240 ...
Page 145
... Figure 17-44. VLM2 Threshold of V 8127D–AVR–02/10 Level Monitor CC VLM THRESHOLD vs. TEMPERATURE 1.7 1.6 1.5 1.4 -40 -20 0 Temperature (C) Level Monitor CC VLM THRESHOLD vs. TEMPERATURE 2.48 2.47 2.46 2.45 2.44 2.43 -40 -20 0 ATtiny4/5/9/10 VLM2:0 = 010 VLM2:0 = 011 Temperature (C) 100 100 145 ...
Page 146
... Figure 17-45. VLM3 Threshold of V 17.11 Current Consumption of Peripheral Units Figure 17-46. ADC Current vs. V ATtiny4/5/9/10 146 Level Monitorr2 CC VLM THRESHOLD vs. TEMPERATURE 3.9 3.8 3.7 3.6 3.5 3.4 -40 - Temperature (C) (ATtiny5/10, only) CC ADC CURRENT vs. V 700 600 500 400 300 200 100 0 1 ...
Page 147
... ANALOG COMPARATOR CURRENT vs 1,5 2 2,5 3 Level Monitor Current vs VLM SUPPLY CURRENT vs. V 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 ATtiny4/5/9/ 3 3 ˚C 5,5 VLM2:0 = 001 VLM2:0 = 010 VLM2:0 = 011 VLM2:0 = 100 VLM2:0 = 000 5 ...
Page 148
... Figure 17-49. Temperature Dependence of VLM Current vs. V 350 300 250 200 150 100 50 Figure 17-50. Watchdog Timer Current vs ATtiny4/5/9/10 148 VLM SUPPLY CURRENT vs 1.5 2 2.5 3 WATCHDOG TIMER CURRENT vs. V 1 VLM2:0 = 001 3 3 (V) CC -40 °C 25 °C 85 °C 5.5 -40 ° ...
Page 149
... The default clock source for the device is always the internal 8 MHz oscillator. Hence, current con- sumption in reset remains unaffected by external clock signals. MINIMUM RESET PULSE WIDTH vs. V 1,5 2 2,5 3 ATtiny4/5/9/10 (0.1 - 1.0 MHz, excluding Current Through the CC CC 0,5 0,6 0,7 ...
Page 150
... Reserved – 0x04 Reserved – 0x03 PUEB – 0x02 PORTB – 0x01 DDRB – 0x00 PINB – ATtiny4/5/9/10 150 Bit 6 Bit 5 Bit 4 Bit Stack Pointer High Byte Stack Pointer Low Byte CPU Change Protection Byte – – – WDRF – ...
Page 151
... Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. The ADC is available in ATtiny5/10, only. 8127D–AVR–02/10 ATtiny4/5/9/10 151 ...
Page 152
... ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set ATtiny4/5/9/10 152 Description Rd ← ← ← ← ← ← ← Rd • ← Rd • ← ← ← Rd ⊕ ← $FF − ← $00 − ← ...
Page 153
... Y ← (Y) ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← Rr (k) ← ← I/O (A) I/O (A) ← Rr STACK ← ← STACK (see specific descr. for Break) (see specific descr. for Sleep) (see specific descr. for WDR) ATtiny4/5/9/10 Operation Flags #Clocks SREG(s) None None T None ...
Page 154
... For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C. 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN) ATtiny4/5/9/10 154 (1) Ordering Code (3) ATtiny4-TSHR (4) ATtiny4-MAHR (3) ATtiny4-TS8R Package Type (2) Package Operational Range 6ST1 ...
Page 155
... This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C. 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad ...
Page 156
... This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C. 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad ...
Page 157
... This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125°C. 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad ...
Page 158
... Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end. 3. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0. Die is facing down after trim/form. Package Drawing Contact: packagedrawings@atmel.com ATtiny4/5/9/10 158 Side View ...
Page 159
... Package Drawing Contact: packagedrawings@atmel.com 8127D–AVR–02/ TITLE 8PAD, 2x2x0.6 mm body, 0.5 mm pitch, 0.9x1.5 mm exposed pad, Saw singulated Thermally enhanced plastic ultra thin dual flat no lead package (UDFN/USON) ATtiny4/5/9/ 0.05 c SIDE VIEW A1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – ...
Page 160
... Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 22.1 ATtiny4 22.1.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. ...
Page 161
... Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 8127D–AVR–02/10 ATtiny4/5/9/10 161 ...
Page 162
... Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.4.3 Rev. A – B Not sampled. ATtiny4/5/9/10 162 8127D–AVR–02/10 ...
Page 163
... Added topside and bottomside marking notes in page 5. Added ESD errata, see 6. Added Lock bits re-programming errata, see 23.3 Rev. 8127B – 08/09 1. Updated document template 2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9 3. Added section: – 4. Updated sections: – – – ...
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... External Programmer for In-System Programming via TPI” on page 98 “Data Memory Map (Byte Addressing)” on page 15 “Number of Words and Pages in the Flash (ATtiny4/5)” on page 110 “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23 “Reset and Interrupt Vectors” on page 36 “ ...
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... CPU Core .................................................................................................. 6 5 Memories ................................................................................................ 14 6 Clock System ......................................................................................... 17 7 Power Management and Sleep Modes ................................................. 23 8127D–AVR–02/10 1.1 Pin Description ..................................................................................................2 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 ...................................4 3.1 Resources .........................................................................................................5 3.2 Code Examples .................................................................................................5 3.3 Data Retention ...................................................................................................5 3.4 Disclaimer ..........................................................................................................5 4.1 Architectural Overview .......................................................................................6 4.2 ALU – Arithmetic Logic Unit ...............................................................................7 4 ...
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... System Control and Reset .................................................................... 27 9 Interrupts ................................................................................................ 36 10 I/O Ports .................................................................................................. 41 11 16-bit Timer/Counter0 ............................................................................ 53 12 Analog Comparator ............................................................................... 82 13 Analog to Digital Converter .................................................................. 84 ATtiny4/5/9/10 ii 8.1 Resetting the AVR ...........................................................................................27 8.2 Reset Sources .................................................................................................27 8.3 Watchdog Timer ..............................................................................................30 8.4 Register Description ........................................................................................32 9.1 Interrupt Vectors ..............................................................................................36 9.2 External Interrupts ...........................................................................................37 9.3 Register Description ........................................................................................38 10 ...
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... Speed ............................................................................................................118 16.4 Clock Characteristics .....................................................................................119 16.5 System and Reset Characteristics ................................................................120 16.6 Analog Comparator Characteristics ...............................................................121 16.7 ADC Characteristics (ATtiny5/10, only) .........................................................121 16.8 Serial Programming Characteristics ..............................................................122 17.1 Supply Current of I/O Modules ......................................................................123 17.2 Active Supply Current ....................................................................................124 ATtiny4/5/9/10 iii ...
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... ATtiny4 ..........................................................................................................154 20.2 ATtiny5 ..........................................................................................................155 20.3 ATtiny9 ..........................................................................................................156 20.4 ATtiny10 ........................................................................................................157 21.1 6ST1 ..............................................................................................................158 21.2 8MA4 .............................................................................................................159 22.1 ATtiny4 ..........................................................................................................160 22.2 ATtiny5 ..........................................................................................................160 22.3 ATtiny9 ..........................................................................................................161 22.4 ATtiny10 ........................................................................................................162 23.1 Rev. 8127D – 02/10 .......................................................................................163 23.2 Rev. 8127C – 10/09 .......................................................................................163 23.3 Rev. 8127B – ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...