ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 83

• Manufacturer Part Number: ATTINY4-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 6SOT-23
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

12.1.2
8127D–AVR–02/10
DIDR0 – Digital Input Disable Register 0
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one, the Analog Comparator interrupt request is enabled.
When written logic zero, the interrupt request is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set, this bit enables the input capture function in Timer/Counter0 to be triggered by the
analog comparator. In this case, the comparator output is directly connected to the input capture
front-end logic, using the noise canceler and edge select features of the Timer/Counter0 input
capture interrupt. To make the comparator trigger the Timer/Counter0 input capture interrupt,
the ICIE1 bit in “TIMSK0 – Timer/Counter Interrupt Mask Register 0” must be set.
When this bit is cleared, no connection between the analog comparator and the input capture
function exists.
• Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the analog comparator interrupt. The
different settings are shown in
Table 12-1.
When changing the ACIS1/ACIS0 bits, the analog comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in “ACSR – Analog Comparator Control and Status Register”.
Otherwise an interrupt can occur when the bits are changed.
• Bits 1:0 – ADC1D, ADC0D: Digital Input Disable
When this bit is set, the digital input buffer on pin AIN1 (ADC1) / AIN0 (ADC0) is disabled and
the corresponding PIN register bit will read as zero. When used as an analog input but not
required as a digital input the power consumption in the digital input buffer can be reduced by
writing this bit to logic one.
Bit
0x17
Read/Write
Initial Value
ACIS1
0
0
1
1
Selecting Source for Analog Comparator Interrupt.
R
7
–
0
ACIS0
0
1
0
1
R
6
–
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
R
5
–
0
12-1.
4
–
R
0
R
3
–
0
R
2
–
0
ADC1D
R/W
1
0
ATtiny4/5/9/10
ADC0D
R/W
0
0
DIDR0
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