ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 22

• Manufacturer Part Number: ATTINY4-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 6SOT-23
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6.5.3
22
ATtiny4/5/9/10
CLKPSR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written at run-time to vary the clock frequency and suit the application
requirements. As the prescaler divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced accordingly. The division factors are given in
Table 6-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be fol-
lowed to change the CLKPS bits:
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected
clock source has a frequency higher than the maximum allowed the application software must
make sure a sufficient division factor is used. To make sure the write procedure is not inter-
rupted, interrupts must be disabled when changing prescaler settings.
Bit
0x36
Read/Write
Initial Value
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
R
7
–
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
R
5
–
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
4
–
0
CLKPS3
R/W
3
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKPS2
R/W
2
0
CLKPS1
R/W
1
1
Clock Division Factor
CLKPS0
8 (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
0
1
128
256
16
32
64
Table
1
2
4
8127D–AVR–02/10
CLKPSR
6-4.