ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 58

• Manufacturer Part Number: ATTINY4-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 6SOT-23
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

11.5
58
Input Capture Unit
ATtiny4/5/9/10
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP0 pin. The time-stamps can then be used to calculate
frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can
be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in
elements of the block diagram that are not directly a part of the Input Capture unit are gray
shaded. The lower case “n” in register and bit names indicates the Timer/Counter number.
Figure 11-5. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag (ICF0) is set at
the same system clock as the TCNT0 value is copied into ICR0 Register. If enabled (ICIE0 = 1),
the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is automatically
cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by software by
writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR0) is done by first reading the low
byte (ICR0L) and then the high byte (ICR0H). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICR0H I/O location it will
access the TEMP Register.
The ICR0 Register can only be written when using a Waveform Generation mode that utilizes
the ICR0 Register for defining the counter’s TOP value. In these cases the Waveform Genera-
ICPn
WRITE
ICRnH (8-bit)
TEMP (8-bit)
Comparator
Analog
ICRn (16-bit Register)
ACO*
ICRnL (8-bit)
ACIC*
DATA BUS
Canceler
Noise
ICNC
(8-bit)
TCNTnH (8-bit)
TCNTn (16-bit Counter)
Detector
ICES
Edge
Figure 11-5 on page
TCNTnL (8-bit)
8127D–AVR–02/10
ICFn (Int.Req.)
58. The