PIC12C672T-04I/SM Microchip Technology, PIC12C672T-04I/SM Datasheet - Page 654

• Manufacturer Part Number: PIC12C672T-04I/SM
• Description: IC MCU OTP 2KX14 A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672T-04I/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
APPENDIX A: I
DS31034A-page 34-2
2
C
This section provides an overview of the Inter-Integrated Circuit (I
A.2 “Addressing I
The I
transfers of up to 100 Kbps. An enhanced specification, or fast mode (400 Kbps) is supported.
Standard and Fast mode devices will operate when attached to the same bus, if the bus operates
at the speed of the slower device.
The I
tion of data. When transmitting data, one device is the “master” which initiates transfer on the bus
and generates the clock signals to permit that transfer, while the other device(s) acts as the
“slave.” All portions of the slave protocol are implemented in the SSP module’s hardware, except
general call support, while portions of the master protocol need to be addressed in the
PIC16CXX software. The MSSP module supports the full implementation of the I
tocol, the general call address, and data transfers upto 1 Mbps. The 1 Mbps data transfers are
supported by some of Microchips Serial EEPROMs.
minology.
In the I
transfer, it first transmits the address of the device that it wishes to “talk” to. All devices “listen” to
see if this is their address. Within this address, a bit specifies if the master wishes to
read-from/write-to the slave device. The master and slave are always in opposite modes (trans-
mitter/receiver) of operation during a data transfer. That is they can be thought of as operating in
either of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-col-
lector in order to perform the wired-AND function of the bus. External pull-up resistors are used
to ensure a high level when no device is pulling the line down. The number of devices that may
be attached to the I
and addressing capability.
OVERVIEW
2
2
C bus is a two-wire serial interface. The original specification, or standard mode, is for data
C interface employs a comprehensive protocol to ensure reliable transmission and recep-
2
C interface protocol each device has an address. When a master wishes to initiate a data
2
C Devices”
2
C bus is limited only by the maximum bus loading specification of 400 pF
discussing the operation of the SSP modules in I
Table A-1
defines some of the I
1997 Microchip Technology Inc.
2
C™) bus, with Subsection
2
C master pro-
2
C mode.
2
C bus ter-