ATMEGA8535L-8JUR Atmel, ATMEGA8535L-8JUR Datasheet - Page 100

• Manufacturer Part Number: ATMEGA8535L-8JUR
• Description: MCU AVR 8K FLASH 8MHZ 44PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8JUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Compare Match Output
Unit
Compare Output Mode and
Waveform Generation
100
ATmega8535(L)
The Compare Output Mode (COM1x1:0) bits have two functions. The waveform genera-
tor uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next
Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig-
ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.
The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of
the general I/O port Control Registers (DDR and PORT) that are affected by the
COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the
internal OC1x Register, not the OC1x pin. If a System Reset occurs, the OC1x Register
is reset to “0”.
Figure 44. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the
waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as
output before the OC1x value is visible on the pin. The port override function is generally
independent of the Waveform Generation mode, but there are some exceptions. Refer
to Table 45, Table 46 and Table 47 for details.
The design of the output compare pin logic allows initialization of the OC1x state before
the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain
modes of operation. See “16-bit Timer/Counter Register Description” on page 110.
The COM1x1:0 bits have no effect on the Input Capture unit.
The Waveform Generator uses the COM1x1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no
action on the OC1x Register is to be performed on the next Compare Match. For com-
pare output actions in the non-PWM modes refer to Table 45 on page 110. For fast
PWM mode refer to Table 46 on page 111, and for phase correct and phase and fre-
quency correct PWM refer to Table 47 on page 111.
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
D
D
D
PORT
DDR
OCnx
Q
Q
Q
1
0
2502K–AVR–10/06
OCnx
Pin