ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 180

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.3.5
4.15.4
4.15.4.1
4.15.4.2
4.15.4.3
4.15.4.4
4.15.4.5
180
Atmel ATA6616/ATA6617
Alternative USI Usage
Start Condition Detector
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
The start condition detector is shown in Figure 4-67. The SDA line is delayed (in the range of
50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only
enabled in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the proces-
sor from the Power-down sleep mode. However, the protocol used might have restrictions on
the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time
set by the CKSEL Fuses (see
48) must also be taken into the consideration. Refer to the USISIF bit description on page 182
for further details.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more com-
pact and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This fea-
ture is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
Section 4.5.1 “Clock Systems and their Distribution” on page
9132D–AUTO–12/10