ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 36

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.5.1
4.3.6
36
Atmel ATA6616/ATA6617
Instruction Execution Timing
SPH and SPL – Stack Pointer Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
the chip. No internal clock division is used.
Figure 4-5
Harvard architecture and the fast access Register File concept. This is the basic pipelining
concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 4-6.
Bit
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an
shows the parallel instruction fetches and instruction executions enabled by the
Result Write Back
SP15
R/W
R/W
SP7
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
15
7
clk
clk
CPU
SP14
CPU
R/W
SP6
R/W
14
6
ISRAM end (See
SP13
SP5
R/W
R/W
13
5
CPU
T1
T1
, directly generated from the selected clock source for
SP12
SP4
R/W
R/W
12
4
Table 4-3 on page
T2
SP11
T2
R/W
R/W
SP3
11
3
SP10
SP2
R/W
R/W
10
2
39)
T3
T3
SP9
SP1
R/W
R/W
9
1
9132D–AUTO–12/10
T4
SP8
SP0
R/W
R/W
T4
8
0
SPH
SPL
®