PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 3

• Manufacturer Part Number: PIC24F16KA102-I/SS
• Description: IC PIC MCU FLASH 16K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: CTMU
2. Module: Resets (BOR)
 2010 Microchip Technology Inc.
Note:
The CTMU and its current source may continue
to operate in Sleep mode. This results in current
consumption in excess of the specifications for
Sleep.
Work around
Clear the CTMU Enable bit (CTMUCON<15>)
prior to entering Sleep mode.
Affected Silicon Revisions
A device Reset may occur if the BOR is disabled
and
(RCON<14> is cleared and then immediately
set).
Work around
It is recommended that several NOP instructions
be added to a BOR disable/enable sequence.
Alternatively, place several instructions or a
short routine between the instructions to disable
and enable the BOR.
Affected Silicon Revisions
A5
A5
X
X
immediately
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B0).
A6
A6
X
X
A7
A7
X
X
B0
B0
X
re-enabled
in
software
PIC24F16KA102 FAMILY
3. Module: Core (ICSP™)
4. Module: Core (Deep Sleep)
Under certain circumstances, a PGC/PGD pin
pair may not function to enter ICSP Program-
ming mode. This has been observed only when
both the following conditions are met:
a)
b)
In these circumstances, the pins do not switch to
a high-impedance state upon entry into
Programming mode, but remain configured as
outputs.
Work around
Choose a PGC/PGD pair with pins that are
always configured as inputs (TRIS bits are set).
Affected Silicon Revisions
Deep Sleep wake-up sources may be ignored if
they occur just prior to entry into Deep Sleep
mode. As a result, the device may enter Deep
Sleep mode when it should not.
Work around
If possible, configure external Deep Sleep
wake-up sources to repeat themselves once. If
the device does enter Deep Sleep, the second
occurrence of the wake-up source will wake the
device.
Alternatively, synchronize the entry into Deep
Sleep with external wake-up sources, where
possible.
Affected Silicon Revisions
A5
A5
X
X
Pin,
(FPOR<5> = 1), and
The pins of the PGEC/PGED pair were con-
figured as digital outputs (corresponding
TRIS bit cleared) in software.
A6
A6
X
RA5,
A7
A7
X
is
B0
B0
configured
DS80473F-page 3
as
MCLR