ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 215

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3
19.4
7766F–AVR–11/10
SPI Data Modes and Timing
Frame Formats
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Table 19-2.
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM
mode has two valid frame formats:
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of
eight, are succeeding, ending with the most or least significant bit accordingly. When a complete
frame is transmitted, a new frame can directly follow it, or the communication line can be set to
an idle (high) state.
• 8-bit data with MSB first
• 8-bit data with LSB first
UCPOLn
BAUD
f
UBRRn
0
0
1
1
OSC
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
XCK
XCK
Data sample (RXD)
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Figure
UCPOLn and UCPHAn Functionality-
19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
UCPHAn
0
1
0
1
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
UCPOL=0
19-2. Note that changing the setting of any of these bits will corrupt
SPI Mode
0
1
2
3
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
ATmega16/32U4
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
UCPOL=1
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