ATMEGA16U4-AU Atmel, ATMEGA16U4-AU Datasheet - Page 359

• Manufacturer Part Number: ATMEGA16U4-AU
• Description: MCU AVR 16K FLASH USB 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U4-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.6.15
7766F–AVR–11/10
Parallel Programming Characteristics
Figure 28-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 28-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
XTAL1
DATA
PAGEL
(DATA, XA0/1, BS1, BS2)
XTAL1
BS1
XA0
XA1
DATA
OE
BS1
XA0
XA1
1. The timing requirements shown in
ing operation.
Data & Contol
Timing Requirements
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
(LOW BYTE)
XTAL1
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 28-7
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
(i.e., t
t
BVWL
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
DVXH
(HIGH BYTE)
READ DATA
t
DATA (High Byte)
WLWH
t
XLPH
WLRL
LOAD DATA
, t
XHXL
ATmega16/32U4
, and t
t
OHDZ
t
PLXH
t
WLBX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
) also apply to load-
ADDR1 (Low Byte)
ADDR1 (Low Byte)
t
WLRH
(1)
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