PIC18F25J11-I/SS Microchip Technology, PIC18F25J11-I/SS Datasheet - Page 35

• Manufacturer Part Number: PIC18F25J11-I/SS
• Description: IC PIC MCU FLASH 32K 2V 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/SS

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.5.1
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTOSC clock will stabilize, typically within 1 μs. Code
execution continues during this shift. There is no
indication that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in more
detail in Section 2.3.1 “Oscillator Control Register”.
The 4x Phase Locked Loop (PLL) can be used with
the internal oscillator block to produce faster device
clock speeds than are normally possible with the
internal oscillator sources. When enabled, the PLL
produces a clock speed up to 32 MHz.
PLL operation is controlled through software. The
control bit, PLLEN (OSCTUNE<6>), is used to enable
or disable its operation. The PLL is available only to
INTOSC when the device is configured to use one of
the INTPLL modes as the primary clock source,
SCS<1:0> = 00 (FOSC<2:0> = 011 or 010).
Additionally, the PLL will only function when the
selected output frequency is either 4 MHz or 8 MHz
(OSCCON<6:4> = 111 or 110).
When configured for one of the PLL enabled modes, set-
ting the PLLEN bit does not immediately switch the
device clock to the PLL output. The PLL requires up to
two milliseconds to start-up and lock, during which time,
the device continues to be clocked. Once the PLL output
is ready, the microcontroller core will automatically
switch to the PLL derived frequency.
2.2.5.2
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as V
ture changes, which can affect the controller operation
in a variety of ways.
The low-frequency INTRC oscillator operates indepen-
dently of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
© 2009 Microchip Technology Inc.
OSCTUNE Register
Internal Oscillator Output Frequency
and Drift
DD
or tempera-
PIC18F46J11 FAMILY
2.2.5.3
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made, and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be required when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may sug-
gest that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared, but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
Finally, an ECCP module can use free-running Timer1
(or Timer3), clocked by the internal oscillator block and
an external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is greater than the calculated time,
the internal oscillator block is running too fast; to
compensate, decrement the OSCTUNE register. If the
measured time is less than the calculated time, the inter-
nal oscillator block is running too slow; to compensate,
increment the OSCTUNE register.
Compensating for INTOSC Drift
DS39932C-page 35