PIC16C432-E/SS Microchip Technology, PIC16C432-E/SS Datasheet - Page 58

• Manufacturer Part Number: PIC16C432-E/SS
• Description: IC MCU CMOS 8BIT 20MHZ 2K 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C432-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164029 - MODULE SKT PROMATEII 20DIP/SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC16C432
9.7
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run even
if the clock on the OSC1 and OSC2 pins of the device
have been stopped, for example, by execution of a
SLEEP
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 9.1).
9.7.1
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, V
FIGURE 9-17:
TABLE 9-8:
DS41140B-page 56
2007h
81h
Legend:
Note 1: Shaded cells are not used by the Watchdog Timer.
Address
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
DD
instruction. During normal operation, a WDT
Watchdog Timer (WDT)
_
and process variations from part to part (see
= Unimplemented location, read as “0”, + = Reserved for future use
WDT PERIOD
Config. bits
OPTION
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
WATCHDOG TIMER BLOCK DIAGRAM
Enable Bit
Watchdog
RBPU
Timer
WDT
Bit 7
—
From TMR0 Clock Source
(Figure 6-6)
INTEDG
BOREN
Bit 6
•
Preliminary
0
1
PSA
M
U
X
T0CS
Bit 5
CP1
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control, by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
9.7.2
It should also be taken in account that under worst case
conditions (V
WDT prescaler), it may take several seconds before a
WDT timeout occurs.
T0SE
Bit 4
CP0
CLRWDT
0
Timeout
MUX
8 - to -1 MUX
WDT
PWRTE
Postscaler
WDT PROGRAMMING
CONSIDERATIONS
Bit 3
PSA
DD
and
•
1
= Min., Temperature = Max., max.
8
SLEEP
WDTE
Bit 2
PS2
To TMR0 (Figure 6-6)
PSA
2002 Microchip Technology Inc.
instructions clear the WDT
PS<2:0>
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0