ATMEGA162-16AUR Atmel, ATMEGA162-16AUR Datasheet - Page 116

MCU AVR 16KB FLASH 16MHZ 44TQFP

ATMEGA162-16AUR

Manufacturer Part Number
ATMEGA162-16AUR
Description
MCU AVR 16KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162-16AUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162-16AUR
Manufacturer:
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Quantity:
10 000
Force Output
Compare
Compare Match
Blocking by TCNTn
Write
Using the Output
Compare Unit
116
ATmega162/V
updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Com-
pare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to
on page
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare
Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the output compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect wave-
form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The Compare Match for the TOP will be ignored and the counter will continue to
0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is down-
counting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
109.
“Accessing 16-bit Registers”
2513K–AVR–07/09

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