ATMEGA162-16AUR Atmel, ATMEGA162-16AUR Datasheet - Page 134

• Manufacturer Part Number: ATMEGA162-16AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Input Capture Register
1 – ICR1H and ICR1L
Input Capture Register
3 – ICR3H and ICR3L
Timer/Counter
Interrupt Mask
Register – TIMSK
134
ATmega162/V
(1)
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers.
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
See “Accessing 16-bit Registers” on page 109.
described in this section. The remaining bits are described in their respective Timer sections.
See “Accessing 16-bit Registers” on page 109.
TOIE1
R/W
R/W
R/W
7
0
7
0
7
0
(See “Interrupts” on page
OCIE1A
R/W
R/W
R/W
6
0
6
0
6
0
57.) is executed when the TOV1 Flag, located in TIFR, is set.
OCIE1B
R/W
R/W
R/W
5
0
5
0
5
0
OCIE2
R/W
R/W
R/W
4
0
4
0
4
0
ICR1[15:8]
ICR3[15:8]
ICR1[7:0]
ICR3[7:0]
57.) is executed when the OCF1A Flag, located in
TICIE1
R/W
R/W
R/W
3
0
3
0
3
0
TOIE2
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
R/W
R/W
R/W
1
0
1
0
1
0
OCIE0
R/W
R/W
R/W
0
0
0
0
0
0
ICR1H
ICR3H
ICR1L
ICR3L
TIMSK
2513K–AVR–07/09