ATMEGA162-16AUR Atmel, ATMEGA162-16AUR Datasheet - Page 79

• Manufacturer Part Number: ATMEGA162-16AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

ATmega162/V
• TOSC1/XCK0/OC3A – Port D, Bit 4
TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter2, pin PD4 is disconnected from the port, and becomes the input of the
inverting Oscillator Amplifier. In this mode, a crystal Oscillator is connected to this pin, and the
pin can not be used as an I/O pin.
XCK0, USART0 External Clock: The Data Direction Register (DDD4) controls whether the clock
is output (DDD4 set (one)) or input (DDD4 cleared (zero)). The XCK0 pin is active only when
USART0 operates in Synchronous mode.
OC3A, Output Compare Match A output: The PD4 pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD4 set (one))
to serve this function. The OC4A pin is also the output pin for the PWM mode timer function.
• INT1/ICP3 – Port D, Bit 3
INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt source.
ICP3, Input Capture Pin: The PD3 pin can act as an Input Capture pin for Timer/Counter3.
• INT0/XCK1 – Port D, Bit 2
INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source.
XCK1, USART1 External Clock: The Data Direction Register (DDD2) controls whether the clock
is output (DDD2 set (one)) or input (DDD2 cleared (zero)). The XCK1 pin is active only when
USART1 operates in Synchronous mode.
• TXD0 – Port D, Bit 1
TXD0, Transmit Data (Data output pin for USART0). When the USART0 Transmitter is enabled,
this pin is configured as an output regardless of the value of DDD1.
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2513K–AVR–07/09