DSPIC33FJ64GS406T-I/MR Microchip Technology, DSPIC33FJ64GS406T-I/MR Datasheet - Page 199

• Manufacturer Part Number: DSPIC33FJ64GS406T-I/MR
• Description: MCU/DSP 16BIT 64KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS406T-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-VQFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.0
The
dsPIC33FJ64GS406/606/608/610 devices provide the
ability to manage power consumption by selectively man-
aging clocking to the CPU and the peripherals. In general,
a lower clock frequency and a reduction in the number of
circuits being clocked constitutes lower consumed power.
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ64GS406/606/608/610 devices can manage
power consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software-Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
The
dsPIC33FJ64GS406/606/608/610 devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
EXAMPLE 10-1:
 2010 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
dsPIC33FJ32GS406/606/608/610
dsPIC33FJ32GS406/606/608/610
of the dsPIC33FJ32GS406/606/608/610
and
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
dsPIC33FJ64GS406/606/608/610
and
PWRSAV INSTRUCTION SYNTAX
Power-Saving
; Put the device into SLEEP mode
; Put the device into IDLE mode
Modes”
and
and
and
Preliminary
10.2
The
dsPIC33FJ64GS406/606/608/610 devices have two spe-
cial power-saving modes that are entered through the
execution of a special PWRSAV instruction. Sleep mode
stops clock operation and halts all code execution. Idle
mode halts the CPU and code execution, but allows
peripheral modules to continue operation. The assem-
bler syntax of the PWRSAV instruction is shown in
Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
10.2.1
The following occur in Sleep mode:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate,
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
• Any peripheral that requires the system clock
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
since the system clock source is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate. This includes the items such as the
input change notification on the I/O ports or
peripherals that use an external clock input.
source for its operation is disabled.
Note:
Instruction-Based Power-Saving
Modes
dsPIC33FJ32GS406/606/608/610
SLEEP MODE
SLEEP_MODE
constants defined in the assembler
include file for the selected device.
and
IDLE_MODE
DS70591C-page 199
are
and