ATMEGA3250P-20AUR Atmel, ATMEGA3250P-20AUR Datasheet - Page 149

• Manufacturer Part Number: ATMEGA3250P-20AUR
• Description: MCU AVR 32K FLASH 20MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250P-20AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.10 Register Description
16.10.1
8023F–AVR–07/09
TCCR2A – Timer/Counter Control Register A
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. If
applying an external clock on TOSC1, the EXCLK bit in ASSR must be set.
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-
dictable prescaler.
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 16-2.
Note:
Bit
(0xB0)
Read/Write
Initial Value
Mode
T2S
0
1
2
3
/128, clk
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
140.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
T2S
Waveform Generation Mode Bit Description
FOC2A
/256, and clk
W
7
0
WGM20
(PWM2)
WGM20
0
1
0
1
R/W
6
0
T2S
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
/1024. Additionally, clk
COM2A1
R/W
5
0
COM2A0
R/W
4
0
WGM21
R/W
3
0
T2S
ATmega325P/3250P
Table 16-2
(1)
TOP
0xFF
0xFF
OCR2A
0xFF
as well as 0 (stop) may be selected.
CS22
R/W
2
0
T2S
and
Update of
OCR2A at
Immediate
TOP
Immediate
BOTTOM
/8, clk
CS21
R/W
1
0
”Modes of Operation”
T2S
CS20
R/W
/32, clk
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR2A
T2S
/64,
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