DSPIC33FJ64GS606T-I/PT Microchip Technology, DSPIC33FJ64GS606T-I/PT Datasheet - Page 118

• Manufacturer Part Number: DSPIC33FJ64GS606T-I/PT
• Description: MCU/DSP 16BIT 64KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS606T-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 6-2:
DS70591C-page 118
Note:
Oscillator Clock
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
Device Status
POR Reset
BOR Reset
SYSRST
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application
6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is
FSCM
When
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges; otherwise,
the device may not function correctly.
The user application must ensure that
the delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to get all operat-
ing parameters within specification.
V
active until V
the V
becomes stable.
of time (T
appropriate level for full-speed operation. After the delay, T
inactive, which in turn, enables the selected oscillator to start generating clock cycles.
Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
ready and the delay, T
DD
BOR
the
1
SYSTEM RESET TIMING
PWRT
threshold and the delay, T
DD
device
) after a BOR. The delay, T
2
crosses the V
T
FSCM
V
POR
exits
POR
, has elapsed.
POR
the
threshold and the delay, T
BOR
Reset
, has elapsed. The delay, T
Preliminary
V
PWRT
BOR
T
, ensures that the system power supplies have stabilized at the
PWRT
T
3
BOR
Reset
Time
T
POR
OSCD
PWRT
, has elapsed.
BOR
has elapsed and the SYSRST becomes
, ensures the voltage regulator output
T
OST
4
 2010 Microchip Technology Inc.
T
LOCK
5
6
Run
DD
T
crosses
FSCM