DSPIC33FJ64GS606T-I/PT Microchip Technology, DSPIC33FJ64GS606T-I/PT Datasheet - Page 178

• Manufacturer Part Number: DSPIC33FJ64GS606T-I/PT
• Description: MCU/DSP 16BIT 64KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS606T-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
The DMA controller features four identical data transfer
channels. Each channel has its own set of control and
STATUS registers. Each DMA channel can be
configured to copy data either from buffers stored in
dual port DMA RAM to peripheral SFRs or from
peripheral SFRs to buffers in DMA RAM.
The DMA controller supports the following features:
• Word or byte sized data transfers.
• Transfers from peripheral to DMA RAM or DMA
• Indirect Addressing of DMA RAM locations with or
• Peripheral Indirect Addressing – In some
• One-Shot Block Transfers – Terminating DMA
• Continuous Block Transfers – Reloading DMA
• Ping-Pong Mode – Switching between two DMA
• Automatic or manual initiation of block transfers.
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
FIGURE 8-1:
DS70591C-page 178
RAM to peripheral.
without automatic post-increment.
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral.
transfer after one block transfer.
RAM buffer start address after every block
transfer is complete.
RAM start addresses between successive block
transfers, thereby filling two buffers alternately.
Note: For clarity, CPU and DMA address buses are not shown.
SRAM
SRAM X-Bus
CPU
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
PORT 1
DMA RAM
CPU Peripheral DS Bus
Peripheral
Non-DMA
Ready
PORT 2
DMA DS Bus
Preliminary
DMA Controller
0
8.1
Each DMAC Channel x (x = 0, 1, 2, or 3) contains the
following registers:
• A 16-bit DMA Channel Control register
• A 16-bit DMA Channel IRQ Select register
• A 16-bit DMA RAM Primary Start Address Offset
• A 16-bit DMA RAM Secondary Start Address
• A 16-bit DMA Peripheral Address register
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of STATUS registers, DMACS0 and
DMACS1, are common to all DMAC channels.
(DMAxCON)
(DMAxREQ)
register (DMAxSTA)
Offset register (DMAxSTB)
(DMAxPAD)
1
Channels
DMA
Peripheral Indirect Address
DMAC Registers
2
3
Peripheral 1
CPU
Ready
DMA
 2010 Microchip Technology Inc.
DMA
Peripheral 3
CPU
Ready
DMA
DMA
Peripheral 2
CPU
Ready
DMA
DMA