PIC16C925-I/PT Microchip Technology, PIC16C925-I/PT Datasheet
PIC16C925-I/PT
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PIC16C925-I/PT Summary of contents
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... CMOS Microcontrollers 2001 Microchip Technology Inc. PIC16C925/926 Data Sheet with LCD Driver Preliminary DS39544A ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.” ...
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... Microchip Technology Inc. PIC16C925/926 Analog Features: • 10-bit 5-channel Analog-to-Digital Converter (A/D) • Brown-out Reset (BOR) Special Microcontroller Features: • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • ...
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... PIC16C925/926 Pin Diagrams PLCC, CLCC RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO LCD V 3 LCD A VDD OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin DS39544A-page PIC16C92X Preliminary 60 RD5/SEG29/COM3 59 RG6/SEG26 58 RG5/SEG25 57 RG4/SEG24 56 RG3/SEG23 ...
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... LCD OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin 2001 Microchip Technology Inc PIC16C92X Preliminary PIC16C925/926 48 RD5/SEG29/COM3 47 RG6/SEG26 46 RG5/SEG25 45 RG4/SEG24 44 RG3/SEG23 43 RG2/SEG22 42 RG1/SEG21 41 RG0/SEG20 40 RF7/SEG19 39 RF6/SEG18 38 RF5/SEG17 37 RF4/SEG16 36 RF3/SEG15 35 RF2/SEG14 34 RF1/SEG13 33 RF0/SEG12 ...
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... Index .......................................................................................................................................................................... 169 On-Line Support ......................................................................................................................................................... 175 Reader Response ...................................................................................................................................................... 176 PIC16C925/926 Product Identification System .......................................................................................................... 177 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... PIC16C925 2. PIC16C926 The PIC16C925/926 series is a family of low cost, high performance, CMOS, fully static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXXX mid-range family. For the PIC16C925/926 family, there are two device “types” as indicated in the device number: 1 ...
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... PIC16C925/926 FIGURE 1-1: PIC16C925/926 BLOCK DIAGRAM 13 Program Counter EPROM Program Memory 8 Level Stack Program 14 Bus Instruction reg Direct Addr 8 Power-up Oscillator Instruction Decode & Start-up Timer Control Power-on Timing Watchdog Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 A/D Synchronous Serial Port DS39544A-page 6 8 Data Bus ...
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... TABLE 1-2: PIC16C925/926 PINOUT DESCRIPTION PLCC, TQFP Pin Name CLCC Pin# Pin# OSC1/CLKIN 24 14 OSC2/CLKOUT 25 15 MCLR RA0/AN0 5 60 RA1/AN1 6 61 RA2/AN2 8 63 RA3/AN3 REF RA4/T0CKI 10 1 RA5/AN4/ RB0/INT 13 4 RB1 12 3 RB2 4 59 RB3 3 58 RB4 68 56 RB5 67 55 RB6 ...
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... PIC16C925/926 TABLE 1-2: PIC16C925/926 PINOUT DESCRIPTION (CONTINUED) PLCC, TQFP Pin Name CLCC Pin# Pin# RD0/SEG00 31 21 RD1/SEG01 32 22 RD2/SEG02 33 23 RD3/SEG03 34 24 RD4/SEG04 35 25 RD5/SEG29/COM3 60 48 RD6/SEG30/COM2 61 49 RD7/SEG31/COM1 62 50 RE0/SEG05 37 26 RE1/SEG06 38 27 RE2/SEG07 39 28 RE3/SEG08 40 29 RE4/SEG09 41 30 RE5/SEG10 ...
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... All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2001 Microchip Technology Inc. PIC16C925/926 1.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4) ...
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... PIC16C925/926 NOTES: DS39544A-page 10 Preliminary 2001 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16C925/926 family has a 13-bit program counter capable of addressing program memory space. For the PIC16C925, only the first (0000h- 0FFFh) are physically implemented. Accessing a loca- tion above the physically implemented addresses will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h ...
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... PIC16C925/926 2.2 Data Memory Organization The data memory is partitioned into four banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 Bank (STATUS<6:5>) 3 (180h-1FFh (100h-17Fh (80h-FFh (00h-7Fh) 00 The lower locations of each Bank are reserved for the Special Function Registers ...
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... FIGURE 2-3: REGISTER FILE MAP — PIC16C925 File Address Indirect addr.(*) Indirect addr.(*) 00h TMR0 01h 02h PCL STATUS 03h FSR 04h PORTA 05h 06h PORTB PORTC 07h PORTD 08h 09h PORTE PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L 0Eh ...
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... PIC16C925/926 FIGURE 2-4: REGISTER FILE MAP— PIC16C926 File Address Indirect addr.(*) Indirect addr.(*) 00h TMR0 01h 02h PCL STATUS 03h FSR 04h PORTA 05h 06h PORTB PORTC 07h PORTD 08h 09h PORTE PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L ...
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... SSPIF CCP1IF T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR2ON SSPEN CKP SSPM3 SSPM2 CCP1X CCP1Y CCP1M3 CCP1M2 CHS2 CHS1 CHS0 GO/DONE Preliminary PIC16C925/926 Value on Details on Bit 1 Bit 0 Power-on page Reset 26 0000 0000 41 xxxx xxxx 25 0000 0000 0001 1xxx 26 xxxx xxxx 29 --0x 0000 ...
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... PIC16C925/926 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION RBPU INTEDG 82h PCL Program Counter (PC) Least Significant Byte 83h STATUS IRP ...
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... COM3 COM3 COM3 COM3 SEG21 SEG20 SEG19 SEG18 COM3 COM3 COM3 COM3 SEG29 SEG28 SEG27 SEG26 (1) COM3 COM3 COM3 COM3 Preliminary PIC16C925/926 Value on Details on Bit 1 Bit 0 Power-on page Reset 26 0000 0000 41 xxxx xxxx 25 0000 0000 0001 1xxx 26 xxxx xxxx — — ...
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... PIC16C925/926 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION RBPU INTEDG 182h PCL Program Counter’s (PC) Least Significant Byte 183h STATUS ...
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... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 R/W-x R/W-x R/W bit Bit is unknown DS39544A-page 19 ...
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... PIC16C925/926 2.3.2 OPTION REGISTER The OPTION register is a readable and writable regis- ter, which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT pin inter- rupt, TMR0, and the weak pull-ups on PORTB. REGISTER 2-2: OPTION REGISTER (ADDRESS 81h, 181h) ...
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... GIE (INTCON<7>). R/W-0 R/W-0 R/W-0 PEIE TMR0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 R/W-0 R/W-0 R/W-x TMR0IF INTF RBIF bit Bit is unknown DS39544A-page 21 ...
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... PIC16C925/926 2.3.4 PIE1 REGISTER This register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 LCDIE ADIE bit 7 bit 7 LCDIE: LCD Interrupt Enable bit 1 = Enables the LCD interrupt 0 = Disables the LCD interrupt bit 6 ...
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... U-0 U-0 R/W-0 ADIF — — SSPIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 R/W-0 R/W-0 R/W-0 CCP1IF TMR2IF TMR1IF bit Bit is unknown DS39544A-page 23 ...
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... PIC16C925/926 2.3.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR external MCLR Reset or WDT Reset. For various RESET conditions, see Table 12-4 and Table 12-5. REGISTER 2-6: PCON REGISTER (ADDRESS 8Eh) U-0 — ...
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... Program Memory Paging PIC16C925/926 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11-bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2-bits of the address are provided by PCLATH< ...
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... PIC16C925/926 2.6 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg- ister. Any instruction using the INDF register actually accesses the register pointed to by the File Select Reg- ister (FSR). Reading the INDF register itself, indirectly (FSR = ’ ...
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... Initiates a read cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a read Legend Readable bit - n = Value at POR reset 2001 Microchip Technology Inc. PIC16C925/926 When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word, which holds the 14-bit ...
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... PIC16C925/926 3.3 Reading the Program Memory A program memory location may be read by writing two bytes of the address to the PMADR and PMADRH reg- isters, and then setting control bit RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. The ...
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... Select Bank1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; RA<7:6> are always ; read as ’0’. 2001 Microchip Technology Inc. PIC16C925/926 FIGURE 4-1: BLOCK DIAGRAM OF PINS RA3:RA0 AND RA5 Data Bus Port CK Q Data Latch ...
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... PIC16C925/926 TABLE 4-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 bit0 TTL RA1/AN1 bit1 TTL RA2/AN2 bit2 TTL RA3/AN3/V bit3 TTL REF RA4/T0CKI bit4 ST RA5/AN4/SS bit5 TTL Legend: TTL = TTL input Schmitt Trigger input TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address ...
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... DD SS From other RB7:RB4 pins RB7:RB6 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). Preliminary PIC16C925/926 BLOCK DIAGRAM OF RB7:RB4 PINS V DD Weak P Pull-up Data Latch D Q I/O ...
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... PIC16C925/926 TABLE 4-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3 bit3 TTL RB4 bit4 TTL RB5 bit5 TTL RB6 bit6 TTL/ST RB7 bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input TABLE 4-4: ...
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... C mode). Input/output port pin or Synchronous Serial Port data out. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 PORTC Data Direction Control Register Preliminary PIC16C925/926 PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE Weak P Pull-up Data Latch D Q I/O (1) pin CK TRIS Latch ...
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... PIC16C925/926 4.4 PORTD and TRISD Registers PORTD is an 8-bit port with Schmitt Trigger input buff- ers. The first five pins are configurable as general pur- pose I/O pins or LCD segment drivers. Pins RD5, RD6 and RD7 can be digital inputs, or LCD segment, or common drivers. ...
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... Digital input pin or Segment Driver31 or Common Driver1. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RD5 RD4 RD3 RD2 RD1 SE20 SE16 SE12 SE9 SE5 Preliminary PIC16C925/926 Function Value on Value on all Bit 0 Power-on other Reset RESETS RD0 0000 0000 0000 0000 1111 1111 1111 1111 SE0 1111 1111 1111 1111 ...
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... PIC16C925/926 4.5 PORTE and TRISE Register PORTE is a digital input only port. Each pin is multi- plexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. Note Power-on Reset, these pins are configured as LCD segment drivers configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared ...
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... Digital input or Segment Driver18. Digital input or Segment Driver19. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RF5 RF4 RF3 RF2 RF1 SE20 SE16 SE12 SE9 SE5 Preliminary PIC16C925/926 PORTF BLOCK DIAGRAM Digital Input/ LCD Output pin Schmitt Trigger Input Buffer Value on Value on all Bit 0 Power-on ...
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... PIC16C925/926 4.7 PORTG and TRISG Register PORTG is a digital input only port. Each pin is multi- plexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. Note Power-on Reset, these pins are configured as LCD segment drivers configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared ...
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... MOVWF PORTB MOVF PORTB,W Instruction write to Fetched PORTB RB7:RB0 Instruction MOVWF PORTB Executed write to PORTB 2001 Microchip Technology Inc. PIC16C925/926 EXAMPLE 4-8: ;Initial PORT settings: PORTB<7:4> Inputs ; ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; ; BCF PORTB, 7 BCF PORTB, 6 BCF STATUS, RP1 ...
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... PIC16C925/926 NOTES: DS39544A-page 40 Preliminary 2001 Microchip Technology Inc. ...
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... Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with the Watchdog Timer (refer to Figure 5-6 for detailed block diagram). 2001 Microchip Technology Inc. PIC16C925/926 bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2. ...
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... PIC16C925/926 FIGURE 5-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE (Program Counter) PC-1 PC Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetched T0 T0+1 TMR0 Instruction Executed FIGURE 5-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1 (Program Counter) PC-1 PC MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W ...
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... External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 2001 Microchip Technology Inc. PIC16C925/926 When a prescaler is used, the external clock input is divided by the asynchronous ripple counter type pres- caler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account ...
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... PIC16C925/926 5.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer (Figure 5-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a pres- ...
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... Bank0 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE RBIE TMR0IF T0CS T0SE PSA PS2 PORTA Data Direction Control Register Preliminary PIC16C925/926 Value on Value on Bit 1 Bit 0 Power-on all other Reset RESETS xxxx xxxx uuuu uuuu 0000 000x 0000 000u INTF RBIF PS1 ...
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... PIC16C925/926 NOTES: DS39544A-page 46 Preliminary 2001 Microchip Technology Inc. ...
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... RC0 will be read as ‘0’. R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 R/W-0 R/W-0 R/W-0 bit Bit is unknown DS39544A-page 47 ...
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... PIC16C925/926 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F /4. The synchronize control bit T1SYNC OSC (T1CON<2>) has no effect since the internal clock is always in sync. 6.2 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS ...
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... TMPL ; ; Re-enable the Interrupt (if required) ; CONTINUE ;Continue with your code 2001 Microchip Technology Inc. PIC16C925/926 6.3.2 READING AND WRITING TMR1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the ...
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... PIC16C925/926 6.4 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscilla- tor is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP primarily intended for a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator ...
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... FIGURE 7-1: Prescaler F /4 OSC 1:1, 1:4, 1:16 2 Note 1: TMR2 register output can be software selected by the SSP Module as the source clock. Preliminary PIC16C925/926 TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF (1) Output RESET TMR2 reg Postscaler Comparator ...
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... PIC16C925/926 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • ...
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... U-0 R/W-0 R/W-0 R/W-0 — CCP1X CCP1Y CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 CCP MODE - TIMER RESOURCE Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 bit 0 ...
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... PIC16C925/926 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1 (Figure 8-1). An event can be selected to be one of the following: • Every falling edge • Every rising edge • Every 4th rising edge • ...
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... TMR1 register pair and starts an A/D conversion. This allows the CCPR1H:CCPR1L register pair to effectively be a 16-bit programmable period register for Timer1. Note: The “special event trigger” from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). Comparator TMR1L Preliminary PIC16C925/926 DS39544A-page 55 ...
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... PIC16C925/926 8.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2001 Microchip Technology Inc. PIC16C925/926 • MHz • 1 • 125 ns • 1 8.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
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... PIC16C925/926 TABLE 8-3: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCON GIE PEIE 10Bh, 18Bh 0Ch PIR1 LCDIF ADIF 8Ch PIE1 LCDIE ADIE 87h TRISC — — PORTC Data Direction Control Register 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register ...
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... Refer to Application Note AN578, "Use of the SSP Module in the I R-0 R-0 R-0 CKE D mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary PIC16C925/926 Multi-Master Environment.” R-0 R-0 R-0 R bit Bit is unknown DS39544A-page 59 ...
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... PIC16C925/926 REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode new byte is received while SSPBUF is holding previous data ...
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... Example 9-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The MOVWF RXDATA instruction (shaded) is only required if the received data is meaningful. 2001 Microchip Technology Inc. PIC16C925/926 EXAMPLE 9-1: BCF BSF LOOP BTFSS SSPSTAT, BF ...
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... PIC16C925/926 To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the ...
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... SDO SDI (SMP = 0) bit7 SSPIF 2001 Microchip Technology Inc. PIC16C925/926 Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set the SPI is used in Slave mode with CKE = ’1’, then the SS pin control must be enabled ...
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... PIC16C925/926 FIGURE 9-5: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 SDI (SMP = 0) bit7 SSPIF TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCON GIE PEIE 10Bh, 18Bh ...
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... Due to the definition of the START and STOP conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low. FIGURE 9-6: SDA S SCL START Condition Description Preliminary PIC16C925/926 2 C bus is START AND STOP CONDITIONS P Change Change STOP of Data of Data ...
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... PIC16C925/926 2 9.2.2 ADDRESSING I C DEVICES There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 9-7). The more complex is the 10-bit address with a R/W bit (Figure 9-8). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this 10-bit address ...
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... S = START Condition From slave to master P = STOP Condition 2001 Microchip Technology Inc. PIC16C925/926 while SCL is high), but occurs after a data transfer Acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information address a dif- ferent slave device ...
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... PIC16C925/926 9.2.4 MULTI-MASTER 2 The I C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 9.2.4.1 Arbitration Arbitration takes place on the SDA line, while the SCL line is high ...
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... A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0 operation. Preliminary PIC16C925/926 2 C opera modes to be selected mode, with the SSPEN bit set, DS39544A-page 69 ...
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... PIC16C925/926 9.3.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be config- ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automati- ...
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... RC3/SCK/SCL should be enabled by setting bit CKP. R ACK SCL held low while CPU responds to SSPIF Cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Preliminary PIC16C925/926 Receiving Data ACK Bus Master terminates transfer ACK is not sent ...
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... PIC16C925/926 9.3.2 MASTER MODE Master mode of operation is supported, in firmware, using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the SSP module is disabled. The STOP and START bits will toggle based on the START and STOP conditions. ...
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... PRIOR_ADDR_MATCH = FALSE; } 2001 Microchip Technology Inc MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear Set RCV_MODE; } Preliminary PIC16C925/926 DS39544A-page 73 ...
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... PIC16C925/926 NOTES: DS39544A-page 74 Preliminary 2001 Microchip Technology Inc. ...
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... A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC16C925/926 The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register0 (ADCON0) • ...
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... PIC16C925/926 REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’ Left justified. 6 Least Significant bits of ADRESL are read as ‘0’. bit 6-4 Unimplemented: Read as '0' bit 3-0 PCFG< ...
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... For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined as T required before next acquisition starts. CHS<2:0> V AIN (Input Voltage PCFG<3:0> PCFG<3:0> Preliminary PIC16C925/926 A/D Result register pair . A minimum wait 100 RA5/AN4 011 RA3/AN3/V + REF 010 RA2/AN2/V ...
Page 80
... PIC16C925/926 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (R ) and the internal sampling ...
Page 81
... When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom- mended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Specifications section. 2001 Microchip Technology Inc. PIC16C925/926 For correct A/D conversions, the A/D conversion clock (T ) must be selected to ensure a minimum ...
Page 82
... PIC16C925/926 10.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital ...
Page 83
... CCP1IF TMR2IF TMR1IF r0rr 0000 r0rr 0000 (1) (1) SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 r0rr 0000 CHS2 CHS1 CHS0 GO/DONE — — PCFG3 PCFG2 PCFG1 Preliminary PIC16C925/926 ADFM = 0000 00 ADRESL Left Justified for a Power-on Reset. The POR, MCLR, Bit 1 Bit 0 BOR ...
Page 84
... PIC16C925/926 NOTES: DS39544A-page 82 Preliminary 2001 Microchip Technology Inc. ...
Page 85
... Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC16C925/926 selecting the number of commons required by the LCD panel, and then specifying the LCD frame clock rate to be used by the panel. Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a clear/dark pixel, respectively ...
Page 86
... PIC16C925/926 FIGURE 11-1: LCD MODULE BLOCK DIAGRAM Data Bus Timing Control Internal RC osc T1CKI F /4 OSC REGISTER 11-2: LCDPS REGISTER (ADDRESS 10Eh) U-0 — bit 7 bit 7-4 Unimplemented: Read as '0' bit 3-0 LP<3:0>: Frame Clock Prescale Selection bits (see Section 11.1.2) ...
Page 87
... Liquid Crystal Display and Terminal Connection COM0 SEG7 SEG6 SEG5 Selected Waveform COM0 - SEG1 Non-selected Waveform 2001 Microchip Technology Inc. PIN COM0 PIN SEG0 PIN SEG1 COM0 - SEG0 1 frame t f Preliminary PIC16C925/926 1/1 V 0/1 V 1/1 V 0/1 V 1/1 V 0/1 V 1/1 V 0/1 V -1/1 V 0/1 V DS39544A-page 85 ...
Page 88
... PIC16C925/926 FIGURE 11-3: WAVEFORMS IN HALF-DUTY CYCLE DRIVE (B TYPE) Liquid Crystal Display and Terminal Connection COM1 COM0 COM0 - SEG0 Selected Waveform COM0 - SEG1 Non-selected Waveform DS39544A-page 86 PIN COM0 PIN COM1 PIN SEG0 PIN SEG1 1 frame t f Preliminary 2/2 V 1/2 V 0/2 V 2/2 V 1/2 V ...
Page 89
... WAVEFORMS IN ONE-THIRD DUTY CYCLE DRIVE (B TYPE) Liquid Crystal Display and Terminal Connection COM2 COM1 COM0 SEG0 SEG2 SEG1 COM0 - SEG1 Selected Waveform COM0 - SEG0 Non-selected Waveform 2001 Microchip Technology Inc. PIC16C925/926 PIN COM0 PIN COM1 PIN COM2 PIN SEG0 PIN SEG1 1 frame t f ...
Page 90
... PIC16C925/926 FIGURE 11-5: WAVEFORMS IN QUARTER-DUTY CYCLE DRIVE (B TYPE) Liquid Crystal Display and Terminal Connection COM3 COM2 COM1 COM0 SEG1 SEG0 COM3 - SEG0 Selected Waveform COM0 - SEG0 Non-selected Waveform DS39544A-page 88 PIN COM0 PIN COM1 PIN COM2 PIN COM3 PIN SEG0 PIN SEG1 ...
Page 91
... CS1:CS0 Nominal kHz RC 2001 Microchip Technology Inc. PIC16C925/926 The second source is the Timer1 external oscillator. This oscillator provides a lower speed clock which may be used to continue running the LCD while the proces- sor is in SLEEP assumed that the frequency pro- vided on this oscillator will be 32 kHz. To use the Timer1 oscillator as a LCD module clock source only necessary to set the T1OSCEN (T1CON< ...
Page 92
... PIC16C925/926 11.1.2 MULTIPLEX TIMING GENERATION The timing generation circuitry will generate one to four common clocks based on the display mode selected. The mode is specified by bits LMUX1:LMUX0 (LCDCON<1:0>). Table 11-1 shows the formulas for calculating the frame frequency. TABLE 11-1: FRAME FREQUENCY FORMULAS ...
Page 93
... FWR CY 2001 Microchip Technology Inc. PIC16C925/926 A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary ( shown in Figure 11-7 ...
Page 94
... PIC16C925/926 11.3 Pixel Control 11.3.1 LCDD (PIXEL DATA) REGISTERS The pixel registers contain bits which define the state of each pixel. Each bit defines one unique pixel. REGISTER 11-3: GENERIC LCDD REGISTER LAYOUT R/W-x R/W-x SEGs SEGs COMc COMc bit 7 bit 7-0 ...
Page 95
... SEG0 Interrupted Frame SLEEP Instruction Execution 2001 Microchip Technology Inc. PIC16C925/926 If a SLEEP instruction is executed and SLPEN = ’0’, the module will continue to display the current contents of the LCDD registers. To allow the module to continue operation while in SLEEP, the clock source must be either the internal RC oscillator or Timer1 external oscillator ...
Page 96
... PIC16C925/926 11.4.1 SEGMENT ENABLES The LCDSE register is used to select the pin function for groups of pins. The selection allows each group of pins to operate as either LCD drivers or digital only pins. To configure the pins as a digital port, the corre- sponding bits in the LCDSE register must be cleared. ...
Page 97
... V 3 LCD V 3 LCD * These values are provided for design guidance only and should be optimized to the application by the designer. 2001 Microchip Technology Inc. PIC16C925/926 pump. The charge pump boosts V 2*V 1 and LCD LCD pump is not operating, Vlcd3 will be internally tied See the Electrical Specifications section for DD charge pump capacitor and potentiometer values ...
Page 98
... PIC16C925/926 11.6 Configuring the LCD Module The following is the sequence of steps to follow to con- figure the LCD module. 1. Select the frame clock prescale using bits LP3:LP0 (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSE register. 3. Configure the LCD module for the following ...
Page 99
... The other is the Power-up Timer (PWRT), which provides a fixed delay (nomi- nal) on power-up only, designed to keep the part in 2001 Microchip Technology Inc. PIC16C925/926 RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. ...
Page 100
... PIC16C925 (4K program memory Code protection off 10 = 0000h to 07FFh code protected (1/2 protected 0000h to 0EFFh code protected (all but last 256 protected) ...
Page 101
... Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external compo- nents may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. Preliminary PIC16C925/926 CERAMIC RESONATORS Ranges Tested: Freq 455 kHz 68 - 100 100 pF 2 ...
Page 102
... PIC16C925/926 12.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used sim- ple oscillator circuit with TTL gates can be built. Pre- packaged oscillators provide a wide operating range and better stability. A well designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance ...
Page 103
... This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 12-3 for various time-out situations. 2001 Microchip Technology Inc. PIC16C925/926 SLEEP. They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in dif- ferent RESET situations, as indicated in Table 12-4 ...
Page 104
... PIC16C925/926 12.4 Power-on Reset (POR), Power-up Timer (PWRT), Brown-out Reset (BOR) and Oscillator Start-up Timer (OST) 12.4.1 POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when V rise is detected (in the range of 1.5V - 2.1V take advantage of the POR, just tie the MCLR pin ...
Page 105
... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as ’0’. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 2001 Microchip Technology Inc. PIC16C925/926 Condition Program STATUS Counter ...
Page 106
... PIC16C925/926 TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Power-on Reset W xxxx xxxx INDF N/A TMR0 xxxx xxxx PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx PORTA --0x 0000 PORTB xxxx xxxx PORTC --xx xxxx PORTD 0000 0000 PORTE 0000 0000 PCLATH ---0 0000 ...
Page 107
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for RESET value for specific condition. 2001 Microchip Technology Inc. PIC16C925/926 MCLR Resets WDT Reset 1111 1111 0000 0000 ...
Page 108
... PIC16C925/926 FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
Page 109
... Interrupts The PIC16C925/926 family has nine sources of interrupt: • External interrupt RB0/INT • TMR0 overflow interrupt • PORTB change interrupts (pins RB7:RB4) • A/D Interrupt • TMR1 overflow interrupt • TMR2 matches period interrupt • CCP1 interrupt • Synchronous serial port interrupt • ...
Page 110
... PIC16C925/926 FIGURE 12-11: INT PIN INTERRUPT TIMING OSC1 CLKOUT 3 4 INT pin 1 INTF Flag 5 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC-1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 T where T CY cycle or a 2-cycle instruction. ...
Page 111
... MOVWF PCLATH SWAPF STATUS_TEMP,W MOVWF STATUS SWAPF W_TEMP,F SWAPF W_TEMP,W 2001 Microchip Technology Inc. PIC16C925/926 The code in the example: e) Stores the W register. f) Stores the STATUS register in bank 0. g) Stores the PCLATH register. h) Executes the ISR code. i) Restores the STATUS register (and bank select bit) ...
Page 112
... PIC16C925/926 12.7 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscil- lator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction ...
Page 113
... Special event trigger (Timer1 in Asynchronous mode using an external clock). 7. LCD module. 2001 Microchip Technology Inc. PIC16C925/926 Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 114
... PIC16C925/926 FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 (4) CLKOUT INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = SLEEP Fetched Instruction SLEEP Inst( Executed Note 1: XT oscillator mode assumed 1024T (drawing not to scale) This delay will not be there for RC osc mode. ...
Page 115
... CALL and GOTO instructions only OPCODE k (literal 11-bit immediate value 2001 Microchip Technology Inc. PIC16C925/926 TABLE 13-1: Field Register file address (0x00 to 0x7F) f Working register (accumulator) W operations. Bit address within an 8-bit file register b Literal field, constant data or label k Don’ ...
Page 116
... PIC16C925/926 TABLE 13-2: PIC16CXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
Page 117
... Description: Words: Cycles Cycle Activity: Write to data W Example Before Instruction: W FSR After Instruction: W FSR Preliminary PIC16C925/926 Add W and f [ label ] ADDWF f [, 127 d (W) + (f) (destination 0111 dfff ffff Add the contents of the W register with register ’f’. If ’d’ the result is stored in the W register. If ’d’ the result is stored back in register ’ ...
Page 118
... PIC16C925/926 ANDLW AND Literal with W Syntax: [ label ] ANDLW Operands 255 Operation: (W) .AND. (k) (W) Status Affected: Z Encoding: 11 1001 Description: The contents of W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register. Words: 1 Cycles Cycle Activity Read Process Decode literal ‘ ...
Page 119
... Before Instruction: PC After Instruction: if FLAG<1> bfff ffff if FLAG<1> Write data register ’f’ 7 Preliminary PIC16C925/926 Bit Test, Skip if Clear [ label ] BTFSC f [, 127 skip if (f<b> None 01 10bb bfff ffff If bit ’b’ in register ’f’ is ’1’, then the next instruction is executed. ...
Page 120
... PIC16C925/926 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f [,b] Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None 01 11bb Encoding: Description: If bit ’b’ in register ’f’ is ’0’, then the next instruction is executed. If bit ’b’ is ’1’, then the next instruc- ...
Page 121
... Operation: Status Affected: 1fff ffff Encoding: Description: Words: Cycles Cycle Activity: Write register data ’f’ Example Before Instruction After Instruction Preliminary PIC16C925/926 Clear W [ label ] CLRW None 00h ( 0001 0xxx xxxx W register is cleared. Zero bit (Z) is set Process Write to Decode Operation ...
Page 122
... PIC16C925/926 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler Status Affected: TO 0000 Encoding: CLRWDT instruction resets the Description: Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. 1 Words: 1 Cycles Cycle Activity: ...
Page 123
... Write to Words: data destination Cycles: Q Cycle Activity: If Skip: (2nd Cycle) Example Before Instruction After Instruction: CNT if CNT PC if CNT PC Preliminary PIC16C925/926 Decrement f, Skip label ] DECFSZ f [, 127 d [0,1] ( (destination); skip if result = 0 None 00 1011 dfff ffff The contents of register ’f’ are decre- mented. If ’ ...
Page 124
... PIC16C925/926 GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands 2047 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None 10 1kkk Encoding: GOTO is an unconditional branch. The Description: eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. ...
Page 125
... Example Q3 Q4 Before Instruction: Process Write to W data destination After Instruction Operation Operation 1 LOOP Preliminary PIC16C925/926 Inclusive OR Literal with W [ label ] IORLW 255 (W) .OR 1000 kkkk kkkk The contents of the W register is OR’ed with the eight-bit literal 'k'. The result is placed in the W register ...
Page 126
... PIC16C925/926 IORWF Inclusive OR W with f Syntax: [ label ] IORWF Operands 127 d [0,1] Operation: (W).OR. (f) (destination) Status Affected 0100 Encoding: Description: Inclusive OR the W register with reg- ister ’f’. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. ...
Page 127
... Encoding: Description: Words: Cycles: Q Cycle Activity Write data register ’f’ Example OPTION Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Example Preliminary PIC16C925/926 No Operation [ label ] NOP None No operation None 00 0000 0xx0 0000 No operation Decode Operation Operation Operation ...
Page 128
... PIC16C925/926 RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None Operation: TOS PC, 1 GIE Status Affected: None 00 0000 Encoding: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by set- ting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction ...
Page 129
... Stack Cycles Cycle Activity: Operation Operation Example Before Instruction: REG1 C After Instruction: REG1 W C Preliminary PIC16C925/926 Rotate Left f through Carry [ label ] RLF f [, 127 d [0,1] See description below C 00 1101 dfff ffff The contents of register ’f’ are rotated one bit to the left through the Carry Flag. If ’ ...
Page 130
... PIC16C925/926 RRF Rotate Right f through Carry Syntax: [ label ] RRF f [,d] Operands 127 d [0,1] Operation: See description below Status Affected 1100 Encoding: Description: The contents of register ’f’ are rotated one bit to the right through the Carry Flag. If ’d’ the result is placed in the W register. If ’ ...
Page 131
... Z After Instruction: REG1 Example 3: Before Instruction: REG1 After Instruction: REG1 Preliminary PIC16C925/926 Subtract W from f [ label ] SUBWF f [, 127 d [0,1] (f) - (W) destination 0010 dfff ffff Subtract (2’s complement method) W register from register 'f the result is stored in the W register the result is stored back in register 'f'. ...
Page 132
... PIC16C925/926 SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f [,d] Operands 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Encoding: 00 1110 Description: The upper and lower nibbles of reg- ister ’f’ are exchanged. If ’d’ the result is placed in W register. If ’d’ the result is placed in register ’ ...
Page 133
... Description: Words Cycles: Process Write to Q Cycle Activity: data W Example Before Instruction: REG W After Instruction: REG W Preliminary PIC16C925/926 Exclusive OR W with f [ label ] XORWF f [, 127 d [0,1] (W) .XOR. (f) destination 0110 dfff ffff Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f' ...
Page 134
... PIC16C925/926 NOTES: DS39544A-page 132 Preliminary 2001 Microchip Technology Inc. ...
Page 135
... Customizable toolbar and key mapping • A status bar • On-line help 2001 Microchip Technology Inc. PIC16C925/926 The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information) • ...
Page 136
... PIC16C925/926 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker ...
Page 137
... Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I and separate headers for connection to an LCD module and a keypad. and Preliminary PIC16C925/926 PIC16C62X, PIC16C71, PIC16C8X, that supports the PIC16C62, ...
Page 138
... PIC16C925/926 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs ...
Page 139
... Debugger Programmers Kits Preliminary PIC16C925/926 á á á á á á á á á Eval and Boards Demo DS39544A-page 137 ...
Page 140
... PIC16C925/926 NOTES: DS39544A-page 138 Preliminary 2001 Microchip Technology Inc. ...
Page 141
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2001 Microchip Technology Inc. (except V , MCLR, and RA4) ......................................... -0. .............................................................................................. 0V to +10V > DIS DD DD Preliminary PIC16C925/926 + 0.3V {( DS39544A-page 139 ) OL ...
Page 142
... PIC16C925/926 FIGURE 15-1: PIC16C925/926 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 15-2: PIC16LC925/926 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2 (6.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10MHz. ...
Page 143
... not included. The current through the resistor can be esti- EXT /2R (mA) with R in kOhm. DD EXT EXT measurement. Preliminary PIC16C925/926 T +85°C for industrial A T +70°C for commercial A T +85°C for industrial A T +70°C for commercial A Conditions = 4 MHz ...
Page 144
... Watchdog Timer PIC16C925/926 D022 I 1 LCD Voltage LCDT Generation with internal RC osc enabled PIC16LC925/926 D022 LCD Voltage Generation with internal RC osc enabled PIC16C925/926 D022A I Brown-out Reset BOR D024 I 1 LCD Voltage LCDT Generation with Timer1 @ 32.768 kHz PIC16LC925/926 D024 LCD Voltage Generation with Timer1 @ 32 ...
Page 145
... not included. The current through the resistor can be esti- EXT /2R (mA) with R in kOhm. DD EXT EXT measurement. Preliminary PIC16C925/926 T +85°C for industrial A T +70°C for commercial A T +85°C for industrial A T +70°C for commercial A Conditions = 3 ...
Page 146
... Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC16C925/926 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages ...
Page 147
... Min V + 0.1 LCDN LCDN — — 200 Tr - 0.05 — 0.05 LCD LCD Tr Tr LCD LCD . Characteristic Min Typ — Rejection — DD PIC16C925/926 1.0 PIC16LC925/926 1.0 Preliminary Units Conditions COM outputs SEG outputs COM outputs SEG outputs kHz V = 5V, -40°C to +85° ...
Page 148
... PIC16C925/926 15.3 Timing Parameter Symbology The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: ...
Page 149
... All specified values are Preliminary PIC16C925/926 Units Conditions MHz XT and RC osc mode MHz HS osc mode kHz LP osc mode MHz RC osc mode MHz XT osc mode MHz HS osc mode ...
Page 150
... DS39544A-page 148 20, 21 Characteristic Min — — — — — Tosc + 200 0 — PIC16C925/926 100 PIC16LC925/926 200 0 PIC16C925/926 — PIC16LC925/926 — PIC16C925/926 — PIC16LC925/926 — OSC Preliminary new value Typ† Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ...
Page 151
... T I/O Hi-impedance from MCLR Low IOZ or Watchdog Timer Reset † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc. PIC16C925/926 Min Typ† Max Units 2 — ...
Page 152
... Prescaler = 2,4,8 Asynchronous PIC16C925/926 46 Tt1L T1CKI Low Synchronous, Prescaler = 1 Time Synchronous, Prescaler = 2,4,8 Asynchronous PIC16C925/926 47 Tt1P T1CKI Input Synchronous Period Asynchronous PIC16C925/926 Ft1 Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment † ...
Page 153
... PWM Mode) Note: Refer to Figure 15-4 for load conditions. TABLE 15-7: CAPTURE/COMPARE/PWM REQUIREMENTS Parameter Symbol Characteristic No. 50 TccL Input Low Time No Prescaler With Prescaler PIC16C925/926 51 TccH Input High Time No Prescaler With Prescaler PIC16C925/926 52 TccP Input Period 53 TccR Output Rise Time 54 ...
Page 154
... PIC16C925/926 FIGURE 15-10: SPI MASTER MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI MSb IN 73 Note: Refer to Figure 15-4 for load conditions. FIGURE 15-11: SPI MASTER MODE TIMING (CKE = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions ...
Page 155
... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. 2001 Microchip Technology Inc MSb BIT6 - - - - - -1 75, 76 MSb IN BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN Preliminary PIC16C925/926 LSb 77 LSb DS39544A-page 153 ...
Page 156
... PIC16C925/926 TABLE 15-8: SPI MODE REQUIREMENTS Param Symbol No. 70 TssL2scH SCK or SCK input TssL2scL 71 TscH SCK input high time (Slave mode) 71A 72 TscL SCK input low time (Slave mode) 72A 73 TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL 74 TscH2diL, Hold time of SDI data input to SCK edge ...
Page 157
... T : STOP condition SU STO Setup time STOP condition HD STO Hold time 2001 Microchip Technology Inc. PIC16C925/926 Min Typ Max Units 100 kHz mode 4700 — — ns 100 kHz mode 4000 — — ns 100 kHz mode 4700 — — ns 100 kHz mode 4000 — ...
Page 158
... PIC16C925/926 2 FIGURE 15-15 BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-4 for load conditions. 2 TABLE 15-10 BUS DATA REQUIREMENTS Parameter Symbol Characteristic No. 100 T Clock high time HIGH 101 T Clock low time LOW 102 T SDA and SCL rise ...
Page 159
... TABLE 15-11: A/D CONVERTER CHARACTERISTICS: PIC16C925/926 (COMMERCIAL, INDUSTRIAL) PIC16LC925/926 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute error ABS A03 E Integral linearity error IL A04 E Differential linearity error DL A05 E Full scale error FS A06 E Offset error OFF A07 E Gain error GN A10 — ...
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... A/D DATA ADRES ADIF GO SAMPLE 133 TABLE 15-12: A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. 130 T A/D clock period PIC16C925/926 AD PIC16LC925/926 PIC16C925/926 PIC16LC925/926 131 T Conversion time (not including S/H time) CNV (Note 1) 132 T Acquisition time ACQ 134 A/D clock start GO 135 T Switching from convert SWC † ...
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... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 159 ...
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... PIC16C925/926 NOTES: DS39544A-page 160 Preliminary 2001 Microchip Technology Inc. ...
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... Standard OTP marking consists of Microchip part number, year code, week code and traceability code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2001 Microchip Technology Inc. PIC16C925/926 Example PIC16C925 -I/PT 0010017 Example PIC16C926/L 0010017 ...
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... PIC16C925/926 Package Marking Information (Continued) 68-Lead CERQUAD Windowed XXXXXXXXXXXXXXX YYWWNNN DS39544A-page 162 Example PIC16C926/CL 0010017 Preliminary 2001 Microchip Technology Inc. ...
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... Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 2001 Microchip Technology Inc. PIC16C925/926 ...
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... PIC16C925/926 68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC #leads= CH2 x 45 CH1 Dimension Limits Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Side 1 Chamfer Height Corner Chamfer 1 Corner Chamfer (others) Overall Width Overall Length Molded Package Width ...
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... Ceramic Package Length Footprint Width Footprint Length Pins each side Lead Thickness Upper Lead Width Lower Lead Width Window Diameter * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-087 Drawing No. C04-097 2001 Microchip Technology Inc. PIC16C925/926 CH1 Units INCHES* MIN NOM MAX n ...
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... PIC16C925/926 NOTES: DS39544A-page 166 Preliminary 2001 Microchip Technology Inc. ...
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... PIC16C925/926 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are listed in Table B-1. TABLE B-1: DEVICE DIFFERENCES Feature PIC16C925 EPROM Program Memory (words) Data Memory (bytes) Note: On 64-pin TQFP, pins RG7 and RE7 are not available. Preliminary ...
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... Data Memory 176 (bytes) A/D Converter 8-bit Resolution (924 only) A/D Converter none (923) Channels 5 (924) 8 (923) Interrupt Sources 9 (924) Brown-out Reset No DS39544A-page 168 PIC16C925/ 926 MHz 4K (925) 8K (926) 176 (925) 336 (926) 10-bit 5 9 Yes Preliminary 2001 Microchip Technology Inc. ...
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... External Parallel Cystal Oscillator ............................ 100 External Series Crystal Oscillator ............................ 100 Interrupt Logic .......................................................... 107 LCD Charge Pump ..................................................... 95 LCD Module ............................................................... 84 LCD Resistor Ladder ................................................. 95 On-Chip Reset Circuit .............................................. 101 PIC16C925/926 Architecture ....................................... 6 PORTA RA3:RA0 and RA5 Port Pins ............................. 29 RA4/T0CKI Pin .................................................. 29 PORTB RB3:RB0 Port Pins ............................................ 31 RB7:RB4 Port Pins ............................................ 31 2001 Microchip Technology Inc ...
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... PIC16C925/926 Code Protection ......................................................... 97, 112 Compare Mode (CCP) Associated Registers ................................................. 58 Block Diagram ............................................................ 55 Pin Configuration ....................................................... 55 Software Interrupt Mode ............................................ 55 Special Event Trigger ................................................. 55 Timer1 Mode .............................................................. 55 Computed GOTO ............................................................... 25 Configuration Bits ............................................................... 97 Configuration Word ............................................................ and AC Characteristics Graphs and Tables ............... 159 DC bit ................................................................................. 19 Development Support ...................................................... 133 Device DC Characteristics ....................................... 141–145 LC Devices ...
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... PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 135 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 136 PICSTART Plus Entry Level Development Programmer ....................................... 135 PIE1 Register ............................................................. 22, 107 Initialization States ................................................... 104 2001 Microchip Technology Inc. PIC16C925/926 Pin Functions MCLR/V ................................................................... 7 PP OSC1/CLKIN ............................................................... 7 OSC2/CLKOUT ........................................................... 7 RA0/AN0 ...................................................................... 7 RA1/AN1 ...................................................................... 7 RA2/AN2 ...................................................................... 7 RA3/AN3/V ...
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... Example Period and Duty Cycle Calculations ........... 57 R R/W bit ................................................................... 66, 70, 71 RBIF bit ...................................................................... 31, 108 RC Oscillator ...................................................... 99, 100, 102 RCV_MODE ...................................................................... 73 Read-Modify-Write ............................................................. 39 Register File ....................................................................... 12 Register File Map PIC16C925 ................................................................ 13 PIC16C926 ................................................................ 14 Registers ADCON0 (A/D Control 0) ........................................... 75 ADCON1 (A/D Control 1) ........................................... 76 CCP1CON (CCP Control) .......................................... 53 Flag ............................................................................ 23 Initialization Conditions .................................... 104–105 INTCON (Interrupt Control) ........................................ 21 LCDCON (LCD Control) ...
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... SSPOV (Receive Overflow Indicator) bit ........................... 60 SSPOV bit .......................................................................... 70 Stack .................................................................................. 25 Overflows ................................................................... 25 Underflow ................................................................... 25 STATUS Register .............................................................. 19 Initialization States ................................................... 104 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 .......................................................... 60 2001 Microchip Technology Inc. PIC16C925/926 T T .................................................................................... 79 AD Timer0 Associated Registers ................................................. 45 Block Diagram ........................................................... 41 Clock Source Edge Select (T0SE Bit) ....................... 20 Clock Source Select (T0CS Bit) ................................ 20 External Clock ...
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... PIC16C925/926 Timer0,Internal Timing ............................................... 42 Wake-up from SLEEP through Interrupt .................. 112 Timing Diagrams and Specifications ................................ 147 Timing Parameter Symbology .......................................... 146 TO bit ................................................................................. 19 TRISA Register .................................................................. 29 Initialization State ..................................................... 104 TRISB Register .................................................................. 31 Initialization State ..................................................... 104 TRISC Register .................................................................. 33 Initialization State ..................................................... 104 TRISD Register .................................................................. 34 Initialization State ..................................................... 104 TRISE Register .................................................................. 36 Initialization State ...
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... Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2001 Microchip Technology Inc. PIC16C925/926 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip’s development systems software products. ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C925/926 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... PIC16C925/926 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X PART NO. Device Temperature Package Range (1) Device PIC16C92X , PIC16C92XT V range 4.0V to 5.5V DD (1) PIC16LC92X , PIC16LC92XT V range 2.5V to 5.5V DD Temperature +85 C (Industrial) Range +85 C (Industrial, tape/reel) ...
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... NOTES: 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 178 ...
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... NOTES: 2001 Microchip Technology Inc. PIC16C925/926 Preliminary DS39544A-page 179 ...
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... Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. ...