PIC16C925-I/PT Microchip Technology, PIC16C925-I/PT Datasheet - Page 63

• Manufacturer Part Number: PIC16C925-I/PT
• Description: IC MCU OTP 4KX14 LCD DVR 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C925-I/PT

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC16C
• No. Of I/o's: 25
• Ram Memory Size: 176Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16PQ640 - ADAPTER DEVICE FOR MPLAB-ICEAC164023 - MODULE SKT PROMATEII 68TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C925I/PT

9.1
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI
• Serial Clock (SCK) RC3/SCK
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) RA5/AN4/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register.
(SSPSTAT<0>),
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully. When the
application software is expecting to receive valid data,
the SSPBUF should be read before the next byte of
data to transfer is written to the SSPBUF. Buffer full bit,
BF (SSPSTAT<0>), indicates when SSPBUF has been
loaded with the received data (transmission is com-
plete). When the SSPBUF is read, bit BF is cleared.
This data may be irrelevant if the SPI is only a transmit-
ter. Generally, the SSP interrupt is used to determine
when the transmission/reception has completed. The
SSPBUF must be read and/or written. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur. Example 9-1 shows the loading of the SSPBUF
(SSPSR) for data transmission. The MOVWF RXDATA
instruction (shaded) is only required if the received data
is meaningful.
SCK)
2001 Microchip Technology Inc.
SPI Mode
Then,
the
and
buffer
interrupt
full detect bit,
flag
bit,
SSPIF
Preliminary
BF
EXAMPLE 9-1:
The block diagram of the SSP module, when in SPI
mode (Figure 9-1), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 9-1:
LOOP
RC4/SDI/SDA
RA5/AN4/SS
RC5/SDO
RC3/SCK/
SCL
BCF
BSF
BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
PIC16C925/926
STATUS, RP1
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
Read
SS Control
Select
TRISC<3>
Edge
SSPM3:SSPM0
LOADING THE SSPBUF
(SSPSR) REGISTER
SSP BLOCK DIAGRAM
(SPI MODE)
Enable
bit0
Select
Edge
SSPBUF reg
SSPSR reg
Clock Select
4
;Select Bank1
;
;Has data been
;received
;(transmit
;complete)?
;No
;Select Bank0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
2
DS39544A-page 61
Prescaler
4, 16, 64
TMR2 Output
Write
Clock
Shift
Data Bus
Internal
2
T
CY