PIC16LC923-04/PT Microchip Technology, PIC16LC923-04/PT Datasheet - Page 113

• Manufacturer Part Number: PIC16LC923-04/PT
• Description: IC MCU OTP 4KX14 LCD DVR 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC923-04/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

14.5
The PIC16C9XX family has up to 9 sources of interrupt:
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts
(pins RB7:RB4)
A/D Interrupt
TMR1 overflow interrupt
TMR2 matches period interrupt
CCP1 interrupt
Synchronous serial port interrupt
LCD Module interrupt
1997 Microchip Technology Inc.
Note:
Interrupts
Interrupt Sources
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
Applicable
923
923
923
923
923
923
923
923
923
Devices
924
924
924
924
924
924
924
924
924
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in various
registers. Individual interrupt bits are set regardless of
the status of the GIE bit. The GIE bit is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function register PIR1. The corresponding interrupt
enable bits are contained in special function register
PIE1, and the peripheral interrupt enable bit is con-
tained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin
or RB Port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends
(Figure 14-15). The latency is the same for one or two
cycle instructions. Individual interrupt flag bits are set
regardless of the status of their corresponding mask bit
or the GIE bit.
when
the
PIC16C9XX
interrupt
DS30444E - page 113
event
occurs