PIC16LC923-04/PT Microchip Technology, PIC16LC923-04/PT Datasheet - Page 77

• Manufacturer Part Number: PIC16LC923-04/PT
• Description: IC MCU OTP 4KX14 LCD DVR 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC923-04/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.3.2
Master mode of operation is supported, in firmware,
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP and START bits will
toggle based on the start and stop conditions. Control
of the I
bus is idle with both the S and P bits clear.
In master mode the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 11-4: REGISTERS ASSOCIATED WITH I
Address
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
13h
93h
14h
94h
87h
Legend:
Note
1997 Microchip Technology Inc.
2
1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.
C bus may be taken when the P bit is set, or the
MASTER MODE
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by SSP in I
Name
INTCON
PIR1
PIE1
SSPBUF
SSPADD
SSPCON
SSPSTAT
TRISC
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I
LCDIF
LCDIE
WCOL
SMP
Bit 7
GIE
—
ADIE
SSPOV
ADIF
PEIE
Bit 6
CKE
—
(1)
(1)
PORTC Data Direction Control Register
SSPEN
Bit 5
T0IE
2
D/A
C mode) Address Register
—
—
INTE
Bit 4
CKP
—
—
P
2
C OPERATION
SSPM3
SSPIE
SSPIF
RBIE
Bit 3
S
11.3.3
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows the
determination of when the bus is free. The STOP (P)
will toggle based on the start and stop conditions. Con-
trol of the I
STAT<4>) is set, or the bus is idle with both the S and
P bits clear. When the bus is busy, enabling the SSP
Interrupt will generate the interrupt when the STOP
condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, they are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
and START (S) bits are cleared from a reset or when
the SSP module is disabled. The STOP and START bits
CCP1IE
CCP1IF
SSPM2
Bit 2
T0IF
R/W
MULTI-MASTER MODE
TMR2IF
TMR2IE
SSPM1
INTF
Bit 1
2
UA
C bus may be taken when bit P (SSP-
TMR1IE
TMR1IF
SSPM0
RBIF
Bit 0
BF
PIC16C9XX
2
C mode.
0000 000x
00-- 0000
00-- 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
--11 1111
Power-on
Value on
Reset
DS30444E - page 77
Value on all
other resets
0000 000u
00-- 0000
00-- 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
--11 1111