PIC16LC923-04/PT Microchip Technology, PIC16LC923-04/PT Datasheet - Page 54

• Manufacturer Part Number: PIC16LC923-04/PT
• Description: IC MCU OTP 4KX14 LCD DVR 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC923-04/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PIC16C9XX
8.5
If the CCP1 module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
DS30444E - page 54
Address
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Note
Note:
1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.
Resetting Timer1 using the CCP
Trigger Output
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by theTimer1 module.
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Name
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
LCDIE
LCDIF
Bit 7
GIE
—
ADIF
ADIE
PEIE
Bit 6
—
(1)
(1)
T1CKPS1
Bit 5
T0IE
—
—
T1CKPS0
INTE
Bit 4
—
—
T1OSCEN
SSPIE
SSPIF
RBIE
Bit 3
8.6
TMR1H and TMR1L registers are not reset on a POR
or any other reset except by the CCP1 special event
trigger.
T1CON register is reset to 00h on a Power-on Reset. In
any other reset, the register is unaffected.
8.7
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
T1SYNC
CCP1IF
CCP1IE
Bit 2
T0IF
Resetting of Timer1 Register Pair
(TMR1H:TMR1L)
Timer1 Prescaler
TMR1CS
TMR2IE
TMR2IF
INTF
Bit 1
TMR1ON
TMR1IF
TMR1IE
RBIF
Bit 0
1997 Microchip Technology Inc.
0000 000x
00-- 0000
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
Power-on
Value on
Reset
0000 000u
00-- 0000
00-- 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
Value on
all other
resets