AT89C51IC2-SLSUM Atmel, AT89C51IC2-SLSUM Datasheet - Page 99

• Manufacturer Part Number: AT89C51IC2-SLSUM
• Description: IC 8051 MCU FLASH 32K 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51IC2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART, SPI, TWI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Registers
4301D–8051–02/08
Table 73. SSCON Register
SSCON - Synchronous Serial Control register (93h)
Table 74. SSDAT (095h) - Syncrhonous Serial Data register (read/write)
Number
Number
CR2
SD7
Bit
Bit
7
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
Mnemonic Description
Mnemonic Description
SSIE
SSIE
CR2
CR1
CR0
SD6
SD7
SD6
SD5
SD4
SD3
SD2
STA
ST0
Bit
Bit
AA
SI
6
6
Control Rate bit 2
See Table 67.
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
Start flag
Set to send a START condition on the bus.
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
Control Rate bit 1
See Table 67.
Control Rate bit 0
See Table 67.
Address bit 7 or Data bit 7.
Address bit 6 or Data bit 6.
Address bit 5 or Data bit 5.
Address bit 4 or Data bit 4.
Address bit 3 or Data bit 3.
Address bit 2 or Data bit 2.
STA
SD5
5
5
STO
SD4
4
4
SD3
SI
3
3
SD2
AA
2
2
CR1
SD1
1
1
CR0
SD0
0
0
99