PIC18F2480-I/SO Microchip Technology, PIC18F2480-I/SO Datasheet
PIC18F2480-I/SO
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... PIC18F2480/2580/4480/4580 Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D © 2007 Microchip Technology Inc. Data Sheet 28/40/44-Pin and nanoWatt Technology Preliminary DS39637C ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4480 16K 8192 PIC18F4580 32K 16384 © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Three External Interrupts • One Capture/Compare/PWM (CCP) module • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): - One, two or four PWM outputs ...
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... PDIP MCLR/V PP RA0/AN0/CV RA1/AN1 RA2/AN2/V RA3/AN3/V RA4/T0CKI RA5/AN4/SS/HLVDIN RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ RD1/PSP1/C1IN- DS39637C-page /RE3 REF REF REF + 2 REF PIC18F2480 4 18 PIC18F2580 /RE3 1 40 REF REF REF Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX ...
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... Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX 44-Pin QFN RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D AV RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 PIC18F4480 28 6 PIC18F4580 PIC18F4480 PIC18F4580 Preliminary NC RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 463 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 463 Index .................................................................................................................................................................................................. 465 The Microchip Web Site ..................................................................................................................................................................... 477 Customer Change Notification Service .............................................................................................................................................. 477 Customer Support .............................................................................................................................................................................. 477 Reader Response .............................................................................................................................................................................. 478 PIC18F2480/2580/4480/4580 Product Identification System ............................................................................................................ 479 DS39637C-page 4 Preliminary © 2007 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Preliminary DS39637C-page 5 ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F2480/2580/4480/4580 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2480/2580/4480/4580 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • ...
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... DS39637C-page 8 1.3 Details on Individual Family Members Devices in the PIC18F2480/2580/4480/4580 family are available in 28-pin (PIC18F2X80) and 40/44-pin (PIC18F4X80) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in six ways: 1 ...
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... Resets (and Delays) RESET Instruction, Stack Underflow MCLR (optional), Programmable High/ Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Packages © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 PIC18F2480 PIC18F2580 DC – 40 MHz DC – 40 MHz 16384 32768 8192 16384 768 1536 256 256 19 ...
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... PIC18F2480/2580/4480/4580 FIGURE 1-1: PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode & Control Internal ...
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... RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Data Bus<8> Data Latch 8 8 Data Memory ( ...
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... PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS Pin Number Pin Name SPDIP, QFN SOIC MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output ...
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... TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 6 3 RA4 T0CKI 4 RA5/AN4/SS/ 7 HLVDIN RA5 AN4 SS HLVDIN ...
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... PIC18F2480/2580/4480/4580 TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RB0/INT0/ AN10 21 18 RB0 INT0 AN10 RB1/INT1/AN8 22 19 RB1 INT1 AN8 RB2/INT2/CANTX 23 20 RB2 INT2 CANTX RB3/CANRX 24 21 RB3 CANRX RB4/KBI0/AN9 25 22 RB4 KBI0 AN9 RB5/KBI1/PGM ...
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... TABLE 1-2: PIC18F2480/2580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name SPDIP, QFN SOIC RC0/T1OSO/T13CKI 11 8 RC0 T1OSO T13CKI RC1/T1OSI 12 9 RC1 T1OSI RC2/CCP1 13 10 RC2 CCP1 RC3/SCK/SCL 14 11 RC3 SCK SCL RC4/SDI/SDA 15 12 RC4 SDI SDA RC5/SDO 16 13 RC5 SDO ...
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... PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 32 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output DS39637C-page 16 ...
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... HLVDIN RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O. I Analog Analog input 0. ...
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... PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RB0/INT0/FLT0 AN10 RB0 INT0 FLT0 AN10 RB1/INT1/AN8 34 10 RB1 INT1 AN8 RB2/INT2/CANTX 35 11 RB2 INT2 CANTX RB3/CANRX 36 12 RB3 CANRX RB4/KBI0/AN9 37 14 RB4 KBI0 AN9 RB5/KBI1/PGM 38 15 ...
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... RC6 TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output Timer1/Timer3 external clock input ...
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... PIC18F2480/2580/4480/4580 TABLE 1-3: PIC18F4480/4580 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN RD0/PSP0/C1IN RD0 PSP0 C1IN+ RD1/PSP1/C1IN RD1 PSP1 C1IN- RD2/PSP2/C2IN RD2 PSP2 C2IN+ RD3/PSP3/C2IN RD3 PSP3 C2IN- RD4/PSP4/ECCP1 P1A RD4 PSP4 ECCP1 P1A RD5/PSP5/P1B 28 3 RD5 PSP5 P1B ...
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... — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I TTL Read control for Parallel Slave Port (see also WR and CS pins) ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F2480/2580/4480/4580 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL Enabled 5 ...
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... PIC18F2480/2580/4480/4580 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... EXT C > EXT © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F2480/2580/4480/4580 2.6 Internal Oscillator Block The PIC18F2480/2580/4480/4580 devices include an internal oscillator block which generates two different clock signals; either can be used as the micro- controller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘ ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2480/2580/4480/4580 devices are shown in Figure 2-8. See Section 24.0 “Special Features of the CPU” for Configuration register details ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS PIC18F2480/2580/4480/4580 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F2480/2580/4480/4580 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction ...
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... Note: See Table 4-2 in Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Real-Time Clock (RTC). Other features may be operat- ing that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 27.2 “ ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F2480/2580/4480/4580 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • ...
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... PIC18F2480/2580/4480/4580 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up ...
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... PIC18F2480/2580/4480/4580 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode PIC18F2480/2580/4480/4580 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F2480/2580/4480/4580 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “ ...
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... PIC18F2480/2580/4480/4580 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F2480/2580/4480/4580 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F2480/2580/4480/4580 REGISTER 4-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F2480/2580/4480/4580 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F2480/2580/4480/4580 4.4 Brown-out Reset (BOR) PIC18F2480/2580/4480/4580 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0, except ‘ ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F2480/2580/ 4480/4580 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms. ...
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... PIC18F2480/2580/4480/4580 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2480/2580/4480/4580 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on a Power-on Reset and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices BSR 2480 2580 4480 4580 INDF2 2480 2580 4480 4580 POSTINC2 2480 2580 4480 4580 POSTDEC2 2480 2580 4480 4580 PREINC2 2480 2580 4480 4580 PLUSW2 2480 2580 4480 4580 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PIR2 2480 2580 4480 4580 2480 2580 4480 4580 PIE2 2480 2580 4480 4580 2480 2580 4480 4580 IPR1 2480 2580 4480 4580 2480 2580 4480 4580 PIR1 2480 2580 4480 4580 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RXB1SIDH 2480 2580 4480 4580 RXB1CON 2480 2580 4480 4580 TXB0D7 2480 2580 4480 4580 TXB0D6 2480 2580 4480 4580 TXB0D5 2480 2580 4480 4580 TXB0D4 2480 2580 4480 4580 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices RXF3SIDL 2480 2580 4480 4580 RXF3SIDH 2480 2580 4480 4580 RXF2EIDL 2480 2580 4480 4580 RXF2EIDH 2480 2580 4480 4580 RXF2SIDL 2480 2580 4480 4580 RXF2SIDH 2480 2580 4480 4580 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (6) B2D1 2480 2580 4480 4580 (6) B2D0 2480 2580 4480 4580 (6) B2DLC 2480 2580 4480 4580 (6) B2EIDL 2480 2580 4480 4580 (6) B2EIDH 2480 2580 4480 4580 (6) B2SIDL 2480 2580 4480 4580 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F2480/2580/4480/4580 TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (6) RXF13EIDL 2480 2580 4480 4580 (6) RXF13EIDH 2480 2580 4480 4580 (6) RXF13SIDL 2480 2580 4480 4580 (6) RXF13SIDH 2480 2580 4480 4580 (6) RXF12EIDL 2480 2580 4480 4580 (6) RXF12EIDH 2480 2580 4480 4580 ...
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... Accessing a location between upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The PIC18F2480 and PIC18F4480 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word PIC18F4580 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
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... PIC18F2480/2580/4480/4580 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... PIC18F2480/2580/4480/4580 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 5.2.2 INSTRUCTION FLOW/PIPELINING An “Instruction Cycle” consists of four Q cycles: Q1 through Q4 ...
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... PIC18F2480/2580/4480/4580 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘ ...
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... The memory space is divided into as many as 16 banks that contain 256 PIC18F2480/2580/4480/4580 devices implement all 16 banks. Figure 5-6 shows the data memory organization for the PIC18F2480/2580/4480/4580 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The ...
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... PIC18F2480/2580/4480/4580 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2480/4480 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh = 0101 00h Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR 3FFh ...
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... PIC18F2480/2580/4480/4580 FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
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... Table 5-1 and Table 5-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES Address Name Address FFFh TOSU ...
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... PIC18F2480/2580/4480/4580 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address F7Fh — F7Eh — F7Dh — F7Ch — F7Bh — F7Ah — F79h — F78h — F77h ECANCON F76h TXERRCNT F75h RXERRCNT F74h COMSTAT F73h CIOCON F72h ...
Page 75
... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address EFFh — EFEh — EFDh — EDDh EFCh — EDCh EFBh — EFAh — EF9h — EF8h — EF7h — EF6h — EF5h — EF4h — EF3h — ...
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... PIC18F2480/2580/4480/4580 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address E7Fh CANCON_RO4 E7Eh CANSTAT_RO4 (2) E7Dh B5D7 (2) E7Ch B5D6 (2) E7Bh B5D5 (2) E7Ah B5D4 (2) E79h B5D3 (2) E78h B5D2 (2) E77h B5D1 (2) E76h B5D0 (2) E75h B5DLC (2) E74h B5EIDL (2) E73h B5EIDH (2) E72h ...
Page 77
... TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name Address DFFh — DFEh — DDEh DFDh — DDDh DFCh TXBIE DDCh DFBh — DDBh DFAh BIE0 DDAh DF9h — DF8h BSEL0 DF7h — DF6h — DF5h — DF4h — ...
Page 78
... PIC18F2480/2580/4480/4580 TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2480/2580/4480/4580 DEVICES (CONTINUED) Address Name D7Fh — D7Eh — D7Dh — D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH ...
Page 79
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
Page 80
... PIC18F2480/2580/4480/4580 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 FSR2H — — FSR2L Indirect Data Memory Address Pointer 2 Low Byte STATUS — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS ...
Page 81
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH EUSART Baud Rate Generator High Byte SPBRG EUSART Baud Rate Generator RCREG EUSART Receive Register TXREG EUSART Transmit Register TXSTA CSRC TX9 TXEN RCSTA SPEN RX9 SREN EEADR ...
Page 82
... PIC18F2480/2580/4480/4580 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (3) PORTE — — (3) PORTD PORTD Data Direction Register PORTC PORTC Data Direction Register PORTB PORTB Data Direction Register (6) (6) PORTA RA7 RA6 PORTA Data Direction Register ECANCON ...
Page 83
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 RXB0CON RXFUL RXM1 RXM0 Mode 0 RXB0CON RXFUL RXM1 RTRRO Mode 1, 2 RXB1D7 RXB1D77 RXB1D76 RXB1D75 RXB1D6 RXB1D67 RXB1D66 RXB1D65 RXB1D5 RXB1D57 RXB1D56 RXB1D55 RXB1D4 RXB1D47 RXB1D46 RXB1D45 RXB1D3 RXB1D37 ...
Page 84
... PIC18F2480/2580/4480/4580 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D0 TXB1D07 TXB1D06 TXB1D05 TXB1DLC — TXRTR TXB1EIDL EID7 EID6 EID5 TXB1EIDH EID15 EID14 EID13 TXB1SIDL SID2 SID1 SID0 TXB1SIDH SID10 SID9 SID8 TXB1CON ...
Page 85
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 RXF3SIDH SID10 SID9 SID8 RXF2EIDL EID7 EID6 EID5 RXF2EIDH EID15 EID14 EID13 RXF2SIDL SID2 SID1 SID0 RXF2SIDH SID10 SID9 SID8 RXF1EIDL EID7 EID6 EID5 RXF1EIDH EID15 EID14 EID13 RXF1SIDL ...
Page 86
... PIC18F2480/2580/4480/4580 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (8) B4D2 B4D27 B4D26 B4D25 (8) B4D1 B4D17 B4D16 B4D15 (8) B4D0 B4D07 B4D06 B4D05 (8) B4DLC — RXRTR RB1 Receive mode (8) B4DLC — TXRTR Transmit mode (8) B4EIDL EID7 EID6 EID5 ...
Page 87
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (8) B2D4 B2D47 B2D46 B2D45 (8) B2D3 B2D37 B2D36 B2D35 (8) B2D2 B2D27 B2D26 B2D25 (8) B2D1 B2D17 B2D16 B2D15 (8) B2D0 B2D07 B2D06 B2D05 (8) B2DLC — RXRTR RB1 Receive mode (8) B2DLC — ...
Page 88
... PIC18F2480/2580/4480/4580 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (8) B0D7 B0D77 B0D76 B0D75 (8) B0D6 B0D67 B0D66 B0D65 (8) B0D5 B0D57 B0D56 B0D55 (8) B0D4 B0D47 B0D46 B0D45 (8) B0D3 B0D37 B0D36 B0D35 (8) B0D2 B0D27 B0D26 B0D25 (8) B0D1 B0D17 B0D16 ...
Page 89
... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 RXF15EIDH EID15 EID14 EID13 RXF15SIDL SID2 SID1 SID0 RXF15SIDH SID10 SID9 SID8 RXF14EIDL EID7 EID6 EID5 RXF14EIDH EID15 EID14 EID13 RXF14SIDL SID2 SID1 SID0 RXF14SIDH SID10 SID9 SID8 RXF13EIDL ...
Page 90
... PIC18F2480/2580/4480/4580 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
Page 91
... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. ...
Page 92
... PIC18F2480/2580/4480/4580 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
Page 93
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 5.4.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For exam- ple, using an FSR to point to one of the virtual registers will not result in successful operations ...
Page 94
... PIC18F2480/2580/4480/4580 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds eight additional two-word commands to the existing PIC18 instruction set: ADDFSR, ADDULNK, CALLW, MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These ...
Page 95
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 000h 060h Bank 0 080h 100h Bank 1 through Bank 14 ...
Page 96
... PIC18F2480/2580/4480/4580 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower half of Access RAM (00h to 7Fh) is mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined “ ...
Page 97
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... PIC18F2480/2580/4480/4580 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 99
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 100
... PIC18F2480/2580/4480/4580 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 101
... MOVF TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 102
... PIC18F2480/2580/4480/4580 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 103
... CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
Page 104
... PIC18F2480/2580/4480/4580 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'32 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA READ_BLOCK ...
Page 105
... These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 3: This bit is available only in Test mode and Serial Programming mode. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 104 Preliminary © 2007 Microchip Technology Inc. ...
Page 107
... EEPROM. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 108
... PIC18F2480/2580/4480/4580 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 109
... BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 110
... PIC18F2480/2580/4480/4580 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “ ...
Page 111
... PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 110 Preliminary © 2007 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB ...
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... PIC18F2480/2580/4480/4580 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
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... INTERRUPTS The PIC18F2480/2580/4480/4580 devices have multi- ple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high- priority level or a low-priority level. The high-priority interrupt vector is at 000008h and the low-priority interrupt vector is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
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... PIC18F2480/2580/4480/4580 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit ...
Page 117
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 118
... PIC18F2480/2580/4480/4580 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 119
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 U-0 ...
Page 120
... PIC18F2480/2580/4480/4580 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 ...
Page 121
... A TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4X80 and reserved in PIC18F2X80 devices. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 122
... PIC18F2480/2580/4480/4580 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 Mode 0 IRXIF WAKIF R/W-0 R/W-0 Mode 1,2 IRXIF WAKIF bit 7 Legend Readable bit -n = Value at POR bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit invalid message has occurred on the CAN bus ...
Page 123
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit clear. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ...
Page 124
... PIC18F2480/2580/4480/4580 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 (1) OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
Page 125
... When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 (1) ERRIE TXB2IE TXB1IE ...
Page 126
... PIC18F2480/2580/4480/4580 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 127
... ECCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 128
... PIC18F2480/2580/4480/4580 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 Mode 0 IRXIP WAKIP R/W-1 R/W-1 Mode 1,2 IRXIP WAKIP bit 7 Legend Readable bit -n = Value at POR bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit ...
Page 129
... For details of bit operation, see Register 4-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 130
... PIC18F2480/2580/4480/4580 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set ...
Page 131
... EN RD Port Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
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... PIC18F2480/2580/4480/4580 TABLE 10-1: PORTA I/O SUMMARY Pin Name Function I/O RA0/AN0/CV RA0 OUT REF IN AN0 IN (1) CV OUT REF RA1/AN1 RA1 OUT IN AN1 IN RA2/AN2/V - RA2 OUT REF IN AN2 REF RA3/AN3/V + RA3 OUT REF IN AN3 REF RA4/T0CKI RA4 OUT IN T0CKI IN RA5/AN4/SS/HLVDIN RA5 OUT ...
Page 133
... Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2X80 devices. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 ...
Page 134
... PIC18F2480/2580/4480/4580 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 135
... OUT IN Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: Available on 40/44-pin devices only. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TRIS Buffer DIG LATB<0> data output. 0 TTL PORTB<0> data input. Weak pull-up available only in this mode. ...
Page 136
... PIC18F2480/2580/4480/4580 TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB Output Latch Register TRISB PORTB Data Direction Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. ...
Page 137
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 138
... PIC18F2480/2580/4480/4580 TABLE 10-5: PORTC I/O SUMMARY Pin Name Function I/O TRIS RC0/T1OSO/ RC0 OUT 0 T13CKI IN 1 T1OSO OUT x T13CKI IN 1 RC1/T1OSI RC1 OUT T1OSI IN x RC2/CCP1 RC2 OUT CCP1 OUT RC3/SCK/SCL RC3 OUT SCK OUT SCL OUT RC4/SDI/SDA RC4 OUT 0 IN ...
Page 139
... TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Output Latch Register TRISC PORTC Data Direction Register © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 Bit 0 ...
Page 140
... PIC18F2480/2580/4480/4580 10.4 PORTD, TRISD and LATD Registers Note: PORTD is only available on PIC18F4X80 devices. PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... P1D OUT 0 Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Buffer DIG LATD<0> data output. ST PORTD<0> data input. DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled) ...
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... PIC18F2480/2580/4480/4580 TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 (1) PORTD RD7 RD6 (1) LATD LATD Output Latch Register (1) TRISD PORTD Data Direction Register (1) TRISE IBF OBF (1) ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. ...
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... PORTE, TRISE and LATE Registers Depending on the particular PIC18F2480/2580/4480/ 4580 device selected, PORTE is implemented in two different ways. For PIC18F4X80 devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6/C1OUT and RE2/CS/AN7/C2OUT) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘ ...
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... PIC18F2480/2580/4480/4580 REGISTER 10-1: TRISE REGISTER (PIC18F4X80 DEVICES ONLY) R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IBF: Input Buffer Full Status bit word has been received and waiting to be read by the CPU ...
Page 145
... RE3 is the only PORTE bit implemented on both PIC18F2X80 and PIC18F4X80 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4X80 devices). 3: These registers are unimplemented on PIC18F2X80 devices. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TRIS Buffer DIG LATE<0> data output PORTE< ...
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... PIC18F2480/2580/4480/4580 10.6 Parallel Slave Port Note: The Parallel Slave Port is only available on PIC18F4X80 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is con- trolled by the 4 upper bits of the TRISE register (Register 10-1) ...
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... PSPIP ADIP ADCON1 — — (1) CMCON C2OUT C1OUT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers are available on PIC18F4X80 devices only. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 146 Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... PIC18F2480/2580/4480/4580 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing (T0CON<5>). In Timer mode, the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhib- ited for the following two instruction cycles ...
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... Note 1: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 150 Preliminary © 2007 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F2480/2580/4480/4580 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
Page 155
... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F2480/2580/4480/4580 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
Page 157
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 158
... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 156 Preliminary © 2007 Microchip Technology Inc. ...
Page 159
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 160
... PIC18F2480/2580/4480/4580 13.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/ postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 161
... Stops Timer3 Note 1: These bits and the ECCP module are available on PIC18F4X80 devices only. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 162
... PIC18F2480/2580/4480/4580 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction FIGURE 14-1: TIMER3 BLOCK DIAGRAM ...
Page 163
... Note 1: These bits are available in PIC18F4X80 devices only. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 162 Preliminary © 2007 Microchip Technology Inc. ...
Page 165
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F2480/2580 devices have one CCP module. PIC18F4480/4580 devices have (Capture/Compare/PWM) modules. CCP1, discussed in this chapter, implements standard Compare and Pulse-Width Modulation (PWM) modes. ECCP1 implements an Enhanced PWM mode. The ECCP implementation is discussed in Section 16.0 “Enhanced Capture/Compare/PWM Module”. ...
Page 166
... PIC18F2480/2580/4480/4580 15.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 15.1.1 ...
Page 167
... CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 15.2.4 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M3:CCP1M0) ...
Page 168
... PIC18F2480/2580/4480/4580 FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 pin Prescaler ÷ CCP1CON<3:0> Q1:Q4 ECCP1CON<3:0> ECCP1 pin Prescaler ÷ DS39637C-page 166 Set CCP1IF T3ECCP1 and Edge Detect T3ECCP1 4 Set ECCP1IF 4 4 T3CCP1 T3ECCP1 and Edge Detect T3ECCP1 T3CCP1 Preliminary TMR3H TMR3L ...
Page 169
... TMR3L T3CCP1 Comparator ECCPR1H ECCPR1L © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 15.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
Page 170
... PIC18F2480/2580/4480/4580 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL (3) RCON IPEN SBOREN IPR1 PSPIP ADIP PIR1 PSPIF ADIF PIE1 PSPIE ADIE (2) IPR2 OSCFIP CMIP (2) PIR2 OSCFIF CMIF (2) PIE2 OSCFIE CMIE TRISB PORTB Data Direction Register ...
Page 171
... A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 FIGURE 15-4: Duty Cycle TMR2 = PR2 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 (PR4) register ...
Page 172
... PIC18F2480/2580/4480/4580 The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. ...
Page 173
... Shaded cells are not used by PWM or Timer2. Note 1: These registers are unimplemented on PIC18F2X80 devices. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE ...
Page 174
... PIC18F2480/2580/4480/4580 NOTES: DS39637C-page 172 Preliminary © 2007 Microchip Technology Inc. ...
Page 175
... ECCP module are the same as described for the standard CCP module. The control register for the Enhanced CCP module is shown in Register 16-1. It differs from the CCP1CON register in PIC18F2480/2580 devices in that the two Most Significant bits are implemented to control PWM functionality. R/W-0 ...
Page 176
... PIC18F2480/2580/4480/4580 In addition to the expanded range of modes available through the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL (Dead-Band Delay) • ECCP1AS (Auto-Shutdown Control) 16.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode ...
Page 177
... PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation ...
Page 178
... PIC18F2480/2580/4480/4580 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the ECCPR1L register and to the ECCP1CON<5:4> bits 10-bit resolution is available. The ECCPR1L contains the eight MSbs and the ECCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle is calculated by the following equation ...
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... Prescale Value) OSC • Duty Cycle = T * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 0 Duty Cycle Period (1) (1) Delay Delay 0 ...
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... PIC18F2480/2580/4480/4580 16.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin (Figure 16-4). This mode can be used for half-bridge ...
Page 181
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 182
... PIC18F2480/2580/4480/4580 FIGURE 16-7: EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION PIC18F2X80/4X80 P1A P1B P1C P1D 16.4.5.1 Direction Change in Full-Bridge Output Mode In the Full-Bridge Output mode, the EPWM1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the application firm- ware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period ...
Page 184
... PIC18F2480/2580/4480/4580 16.4.6 PROGRAMMABLE DEAD-BAND DELAY Note: Programmable dead-band delay is not implemented in PIC18F2X80 devices with standard CCP modules. In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are ...
Page 185
... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on PIC18F2X80 devices; maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘ ...
Page 186
... PIC18F2480/2580/4480/4580 16.4.7.1 Auto-Shutdown and Auto-Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 187
... P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 16.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states ...
Page 188
... PIC18F2480/2580/4480/4580 TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN SBOREN IPR1 PSPIP ADIP PIR1 PSPIF ADIF PIE1 PSPIE ADIE (3) IPR2 OSCFIP CMIP (3) PIR2 OSCFIF CMIF (3) PIE2 OSCFIE CMIE TRISB PORTB Data Direction Register ...
Page 189
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 190
... PIC18F2480/2580/4480/4580 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
Page 191
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 (2) (3) CKP ...
Page 192
... PIC18F2480/2580/4480/4580 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 193
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 194
... PIC18F2480/2580/4480/4580 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
Page 195
... Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output ...
Page 196
... PIC18F2480/2580/4480/4580 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 197
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2X80 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
Page 198
... PIC18F2480/2580/4480/4580 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
Page 199
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2007 Microchip Technology Inc. PIC18F2480/2580/4480/4580 2 C™ MODE) R-0 R-0 ...
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... PIC18F2480/2580/4480/4580 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I ...