PIC18F2480-I/SO Microchip Technology, PIC18F2480-I/SO Datasheet - Page 470

• Manufacturer Part Number: PIC18F2480-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2480-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
Enhanced Capture/Compare/PWM (ECCP) .................... 173
Enhanced PWM Mode. See PWM (ECCP Module). ........ 175
Enhanced Universal Synchronous Receiver
Equations
Errata ................................................................................... 5
Error Recognition Mode ................................................... 324
EUSART
Extended Instruction Set
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ............................................ 343, 355
Fast Register Stack ............................................................ 64
Firmware Instructions ....................................................... 361
Flash Program Memory ...................................................... 95
DS39637C-page 468
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 174
Pin Configurations for ECCP Modes ........................ 174
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 174
Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 252
A/D Minimum Charging Time ................................... 252
Asynchronous Mode ................................................ 236
Baud Rate Generator (BRG)
Synchronous Master Mode ...................................... 242
Synchronous Slave Mode ........................................ 245
ADDFSR .................................................................. 404
ADDULNK ................................................................ 404
CALLW ..................................................................... 405
MOVSF .................................................................... 405
MOVSS .................................................................... 406
PUSHL ..................................................................... 406
SUBFSR .................................................................. 407
SUBULNK ................................................................ 407
Interrupts in Power-Managed Modes ....................... 356
POR or Wake-up from Sleep ................................... 356
WDT During Oscillator Failure ................................. 355
Associated Registers ............................................... 103
Control Registers ....................................................... 96
Associated Registers, Receive ........................ 239
Associated Registers, Transmit ....................... 237
Auto-Wake-up on Sync Break .......................... 240
Break Character Sequence .............................. 241
Receiver ........................................................... 238
Setting up 9-Bit Mode with
Transmitter ....................................................... 236
Associated Registers ....................................... 231
Auto-Baud Rate Detect .................................... 234
Baud Rate Error, Calculating ........................... 231
Baud Rates, Asynchronous Modes .................. 232
High Baud Rate Select (BRGH Bit) .................. 231
Operation in Power-Managed Mode ................ 231
Sampling .......................................................... 231
Associated Registers, Receive ........................ 244
Associated Registers, Transmit ....................... 243
Reception ......................................................... 244
Transmission .................................................... 242
Associated Registers, Receive ........................ 246
Associated Registers, Transmit ....................... 245
Reception ......................................................... 246
Transmission .................................................... 245
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Address Detect ........................................ 238
Preliminary
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 382
H
Hardware Multiplier
High/Low-Voltage Detect ................................................. 267
HLVD. See High/Low-Voltage Detect. ............................. 267
I
I/O Ports ........................................................................... 129
I
2
C Mode (MSSP)
Erase Sequence ...................................................... 100
Erasing .................................................................... 100
Operation During Code-Protect ............................... 103
Reading ..................................................................... 99
Table Pointer
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing To ................................................................ 101
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
Applications ............................................................. 270
Characteristics ......................................................... 430
Current Consumption ............................................... 269
Effects of a Reset .................................................... 271
Operation
Setup ....................................................................... 269
Start-up Time ........................................................... 269
Typical Application ................................................... 270
Acknowledge Sequence Timing .............................. 220
Baud Rate Generator .............................................. 213
Bus Collision
Clock Arbitration ...................................................... 214
Clock Stretching ....................................................... 206
Clock Synchronization and the
Effect of a Reset ...................................................... 221
General Call Address Support ................................. 210
I
Master Mode ............................................................ 211
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 221
Operation ................................................................. 200
2
C Clock Rate w/BRG ............................................. 213
Boundaries Based on Operation ....................... 98
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
Associated Registers ....................................... 271
During Sleep .................................................... 271
During a Repeated Start Condition .................. 224
During a Stop Condition .................................. 225
10-Bit Slave Receive Mode (SEN = 1) ............ 206
10-Bit Slave Transmit Mode ............................ 206
7-Bit Slave Receive Mode (SEN = 1) .............. 206
7-Bit Slave Transmit Mode .............................. 206
CKP Bit (SEN = 1) ........................................... 207
Operation ......................................................... 212
Reception ........................................................ 217
Repeated Start Condition Timing .................... 216
Start Condition ................................................. 215
Transmission ................................................... 217
Transmit Sequence ......................................... 212
and Arbitration ................................................. 221
© 2007 Microchip Technology Inc.