AT89C51RE2-SLRUM Atmel, AT89C51RE2-SLRUM Datasheet - Page 94

• Manufacturer Part Number: AT89C51RE2-SLRUM
• Description: MCU 8051 128K FLASH 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Serial I/O Port
Framing Error
Detection
94
AT89C51RE2
The serial I/O ports in the AT89C51RE2 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1,
2 and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Both serial I/O port include the following enhancements:
•
•
As these improvements apply to both UART, most of the time in the following lines, there won’t
be any reference to UART_0 or UART_1, but only to UART, generally speaking.
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 36)
for UART 0 or set SMOD0_1 in BDRCON_1 register for UART 1 (See Figure 37).
Figure 36. UART 0 Framing Error Block Diagram
Figure 37. UART 1 Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
68.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See
Figure 38 and Figure 39).
Framing error detection
Automatic address recognition
SM0_1/FE_1
SM0D1_1SMOD0_1
SM0/FE
SM0D1
SMOD0
SM1_1
SM1
SM2_1
SM2
-
-
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART 0 mode control (SMOD0 = 0)
To UART 0 framing error control
Set FE_1 bit if stop bit is 0 (framing error) (SMOD0_1 = 1)
SM0 to UART 1 mode control (SMOD0_1 = 0)
To UART 1 framing error control
REN_1
BRR_1
REN
POF
TBCK_1 RBCK_1 SPD_1
TB8_1
GF1
TB8
RB8_1
RB8
GF0
TI_1
PD
TI
SRC_1
RI_1
IDL
RI
SCON_0 (98h)
SCON_1 (C0h)
PCON (87h)
BDRCON_1 (87h)
7663E–8051–10/08