PIC18F2480-I/SP Microchip Technology, PIC18F2480-I/SP Datasheet - Page 239

• Manufacturer Part Number: PIC18F2480-I/SP
• Description: IC PIC MCU FLASH 8KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2480-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/MSSP/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.1.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 19-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN/J2602 bus Sync
character) in order to calculate the proper bit rate. The
measurement is taken over both a low and a high bit
time in order to minimize any effects caused by asym-
metry of the incoming signal. After a Start bit, the
SPBRG begins counting up, using the preselected
clock source on the first rising edge of RX. After eight
bits on the RX pin or the fifth rising edge, an accumu-
lated value totalling the proper BRG period is left in the
SPBRGH:SPBRG register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 19-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock can be configured by the
BRG16 and BRGH bits. The BRG16 bit must be set to
use both SPBRG1 and SPBRGH1 as a 16-bit counter.
This allows the user to verify that no carry occurred for
8-bit modes by checking for 00h in the SPBRGH
register. Refer to Table 19-4 for counter clock rates to
the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
© 2009 Microchip Technology Inc.
AUTO-BAUD RATE DETECT
PIC18F2480/2580/4480/4580
TABLE 19-4:
19.1.3.1
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
BRG16
Note 1: If the WUE bit is set with the ABDEN bit,
0
0
1
1
2: It is up to the user to determine that the
3: To maximize baud rate range, it is recom-
BRGH
Auto-Baud Rate Detection will occur on
the byte following the Break character.
incoming character baud rate is within the
range of the selected BRG clock source.
Some
frequency and EUSART baud rates are
not possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when
Detection feature.
mended to set the BRG16 bit if the
auto-baud feature is used.
ABD and EUSART Transmission
0
1
0
1
BRG COUNTER
CLOCK RATES
using
combinations
BRG Counter Clock
the
F
F
F
F
OSC
OSC
OSC
OSC
Auto-Baud
DS39637D-page 239
/512
/128
/128
/32
of
oscillator
Rate