PIC18F2480-I/SP Microchip Technology, PIC18F2480-I/SP Datasheet - Page 245

• Manufacturer Part Number: PIC18F2480-I/SP
• Description: IC PIC MCU FLASH 8KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2480-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/MSSP/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 19-7:
TABLE 19-6:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
Reserved in PIC18F2X80 devices; always maintain these bits clear.
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
Start
bit
bit 0
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
PIC18F2480/2580/4480/4580
bit 7/8
Stop
INT0IE
CREN
SYNC
bit
SCKP
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
Word 2
RCREG
FERR
Bit 2
—
Stop
bit
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Start
WUE
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
bit 7/8
TX9D
DS39637D-page 245
RBIF
Bit 0
Stop
bit
on Page:
Values
Reset
55
58
58
58
57
57
57
57
57
57