DSPIC30F6012-20E/PF Microchip Technology, DSPIC30F6012-20E/PF Datasheet
DSPIC30F6012-20E/PF
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... ICD Product ID Running ICD Self Test ...Passed MPLAB ICD 2 Ready The errata described in this section will be addressed in future revisions of dsPIC30F6011, dsPIC30F6012, dsPIC30F6013 and dsPIC30F6014 silicon. Silicon Errata Summary The following list summarizes the errata described in this document: 1. ...
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... SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. The following sections will describe the erratas and the work around to these erratas, where they may apply. © 2008 Microchip Technology Inc. ® DSC ...
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... MCU Multiply instruction, MUL.UU. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3. Module: MAC class Instructions with +4 Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1 ...
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... Result in W3 (3) SR<1:0> bits , Result in W3 (3) SR<1:0> bits (3) SR<1:0> bits , Result in W4 (3) SR<1:0> bits , Result in W2 (3) SR<1:0> bits (4) SR<15:10> bits CORRECT RESULTS ;Load PSVPAG register ;indirect PSV access ;from 0x000200 ;works ok ;from program memory ;results are ok! © 2008 Microchip Technology Inc. ...
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... INTCON1, #ADDRERR ;Clear the ;Address Error ;trap flag bit reset ;Software reset © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 8. Module: Y Data Space Dependency When an instruction that writes to a location in the address range of Y data memory (addresses between 0x1800 and 0x27FF) is immediately followed by a MAC type DSP instruction that reads a location also resident in Y data memory, the two operations will not be executed as specified ...
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... RETFIE Loop REPEAT DISI BEFORE RETFIE ;Timer1 ISR ;This line optional ;This line optional ;Another interrupt occurs ;here and it is processed ;correctly RAISE IPL BEFORE RETFIE ;Timer1 ISR ;Another interrupt occurs ;here and it is processed ;correctly © 2008 Microchip Technology Inc. ...
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... Work around None. The application may only use the 1:1 prescaler for 32-bit timers. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 13. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: • ...
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... An example of loading the DCI transmit buffers for the configuration above is shown in Example 11. A timing diagram in Figure 1 illustrates the various signals for this example. A similar rule may be applied to reading the received data from the RXBUFn SFRs. © 2008 Microchip Technology Inc. intended for ...
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... Data loaded into TXBUF0 contains 15 MSbs of the actual 16-bit data to be transmitted, while the MSb of TXBUF0 is cleared. 4: Not all serial clock pulses are shown in this timing diagram. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Frame Synch and first data bit sampled here ...
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... MIPS prior to the erase operation. To ensure that the device is operating at less than 10 MIPS, the application may post-scale the system clock or switch to the internal FRC oscillator. During Row Erase pin using a voltage regulator DD greater than or equal to 4.2V, DD pin and ground. © 2008 Microchip Technology Inc. ...
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... Use 8x PLL or 16x PLL mode of operation and set final device clock speed using the POST<1:0> oscillator postscaler control bits (OSCCON<7:6>). 2. Use the EC without PLL Clock mode with a suitable clock frequency equivalent 4x PLL clock rate. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 DD dsPIC30FXXX-30I dsPIC30FXXX-20I 30 — to obtain ...
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... SET_CPU_IPL macro. For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as shown in Example 16. This macro is not distributed with the compiler the CPU IPL, the macros and © 2008 Microchip Technology Inc. ...
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... Module: 8x PLL Mode If 8x PLL mode is used, the input frequency range is 5-10 MHz instead of 4-10 MHz. Work around None PLL is used, ensure that the input crystal or clock frequency is 5 MHz or greater. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 \ \ \ \ DS80198J-page 13 ...
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... Sleep mode. Example 17 demonstrates the work around described above would apply to a dsPIC30F6014 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function call would be following the or _GotoSleep © 2008 Microchip Technology Inc. ...
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... Note: The above work around is recommended for users for whom application hardware changes are not possible. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode ...
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... If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. © 2008 Microchip Technology Inc slave interrupt 2 C nodes. ...
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... Clock Failure Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 30. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page ...
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... For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. DS80198J-page module is that have 2 C © 2008 Microchip Technology Inc. ...
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... Port – Port Pin Multiplexed with IC1). Revision H (5/2008) 2 Added silicon issues 28 and 29 (I C), and 30 (Timer). Revision J (9/2008) 2 Replaced issues 25 and with issue 33 (I Added silicon issues 29 (PLL Lock Status Bit), 30 (PSV 2 Operations) and 31-33 (I C). © 2008 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 2 C), and 27 (I/O 2 C). DS80198J-page 19 ...
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... NOTES: DS80198J-page 20 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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