DSPIC30F6012-20E/PF Microchip Technology, DSPIC30F6012-20E/PF Datasheet
DSPIC30F6012-20E/PF
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DSPIC30F6012-20E/PF Summary of contents
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... Microchip corporate web site (www.microchip.com). TABLE 1: SILICON DEVREV VALUES Part Number dsPIC30F6011 dsPIC30F6012 dsPIC30F6013 dsPIC30F6014 Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. 2: Refer to the “ ...
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... In Slave mode, the DCI module does not function correctly when data communication is configured to start one serial clock after the frame synchronization pulse. The DCI module should not be stopped when the device enters Idle mode. Affected (1) Revisions © 2010 Microchip Technology Inc. ...
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... CAN RX Filters 3, 34. 4 and 5 Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Issue Summary Read operations performed on CAN module Special Function Registers (SFRs) may yield incorrect results at operation over 20 MIPS. ...
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... The device exhibits I PD arounds are required to achieve I in this range the ADC module enabled state when the device enters Sleep Mode, the power-down current (I exceed the device data sheet specifications. Affected Revisions the device may PD © 2010 Microchip Technology Inc. (1) X ...
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... MUL.UU. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 3. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using +4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1 ...
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... BCD number mov.b #0x80, w1 ;Second BCD number add.b w0, w1, w2 ;Perform addition bra NC, L0 ;If C set daw.b w2 ;If not, do DAW and bset.b SR, #C ;set the carry bit bra L1 ;and exit L0:daw.b w2 L1: .... Affected Silicon Revisions DS80456D-page 6 © 2010 Microchip Technology Inc. ...
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... RAM register prior to performing the operations listed in Table 3. The work around for Example 2 is demonstrated in Example 3. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 These instructions are identified in Table 3. Example 2 demonstrates a scenario where this occurs. ...
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... EXAMPLE 5: TRAP SERVICE ROUTINE __AddressError: bclr RCON, #TRAPR ;Clear the Trap ;Reset Flag Bit bclr INTCON1, #ADDRERR ;Clear the ;Address Error ;trap flag bit reset ;Software reset Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Y data memory. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 9. Module: Interrupt Controller Catastrophic accumulator overflow traps are enabled as follows: - COVTE (INTCON1<8> SATA/SATB (CORCON <7:6> carry generated out of bit 39 in the accumulator causes a catastrophic overflow of the accumulator since the sign bit has been destroyed ...
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... DISI counter decrements to zero and the next DISI instruction. Alternatively, make sure that subsequent DISI instructions are called before the DISI counter decrements to zero. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 14. Module: ADC Input channel scanning allows the ADC to acquire and convert signals on a selected set of “MUX A” input pins in sequence. This function is controlled by the CSCNA bit (ADCON2<10>) and the ADCSSL SFR. ...
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... W1, W1 MOV W0, TXBUF0 MOV W1, TXBUF1 MOV My2ndTxDataWord, W0 RRC W0, W0 RRC W1, W1 MOV W0, TXBUF2 MOV W1, TXBUF3 Frame Synch and first data bit sampled here LSb LSb + 1 Data from TXBUF1 channel. In order DCI SLAVE WORK AROUND Time Slot 1 © 2010 Microchip Technology Inc. ...
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... C1RXF0SIDL first SFR read mov C1RXF0SIDL second SFR read © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: For C Language Source Code For C programmers, the MPLAB C30 v1.20.02 toolsuite provides a built-in function that may be incorporated in the application source code. This function may be used to read any CAN module SFRs ...
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... POST<1:0> oscillator postscaler control bits (OSCCON<7:6>). 2. Use the EC without PLL Clock mode with a suitable equivalent 4x PLL clock rate. Affected Silicon Revisions dsPIC30FXXX-20E 20 — — 2.5V-3.0V, the 4x PLL input DD is 3.0V-3.6V, the 4x PLL input DD clock frequency to obtain the B2 X © 2010 Microchip Technology Inc. ...
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... RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to) #include "p30fxxxx.h" int save_to; SET_AND_SAVE_CPU_IPL (save_to RESTORE_CPU_IPL (save_to) © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: For C Language Source Code For applications using the C language, MPLAB C30 versions 1.32 and higher provide several generic term macros for modifying the CPU IPL. The ...
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... Module: PLL If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. shown in Work around None PLL is used, ensure that the input crystal or clock frequency is 5 MHz or greater. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... NOP instructions .rept 31 NOP .endr ; Place SLEEP instruction in the last word of program memory PWRSAV #0 © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 This can be accomplished by replacing all occurrences of the PWRSAV #0 instruction with a function call to a suitably aligned subroutine. The address( ) attribute provided by the MPLAB ASM30 assembler can be utilized to correctly align the instructions in the subroutine ...
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... Note: The above work around is recommended for users for whom application hardware changes are possible, and also for users whose includes a 32 kHz LP Oscillator crystal. Affected Silicon Revisions Section 29. “Oscillator” application hardware already B2 X © 2010 Microchip Technology Inc. ...
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... This will also clear the RBF flag Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that ...
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... C language, MPLAB C30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 tool suite for further details. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 33. Module: I When the I I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I with the a bus collision in a multi-master configuration ...
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... Auto-convert option is not chosen as the conversion trigger SSRC (ADCON1<7:5>) is not equal to ‘111’ - SAMC (ADCON3<12:8>) is equal to ‘00000’ Work around Set the value of the SAMC bits to anything other than ‘00000’. The module will now operate as specified. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Results are shown here for the PWM1H and PWM1L pins only. Similar results will be observed for any other pair of complementary output pins (PWM2H/L, PWM3H/L and PWM4H/L) and any other chosen duty cycle. © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 40. Module: PWM The output override function of the PWM module, controlled by the OVDCON register and the OSYNC bit (PWMCON2< ...
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... ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV instruction. Affected Silicon Revisions DS80456D-page 24 to values PD +/RA10 pin REF specifications #0 © 2010 Microchip Technology Inc. ...
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... Param Symbol Characteristic No. V Input Low Voltage IL DI19 SDA, SCL V Input High Voltage IH DI29 SDA, SCL © 2010 Microchip Technology Inc. dsPIC30F6011/6012/6013/6014 specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) Operating temperature Min Typ Max V — 0.8 SS 2.1 — ...
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... Added Affected Revisions table to issue 41 (CPU). Rev C Document (2/2010) Updated silicon issue 22 (Interrupt Controller). Rev D Document (6/2010) Added silicon issue 42 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). DS80456D-page 26 2 C), 28 (Timer), 2 C), 34 (CAN), © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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