W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 25

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Mnemonic: SCON
Serial Data Buffer
Mnemonic: SBUF
BIT
7
6
5
4
3
2
1
0
Bit:
NAME
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
7
SBUF.7
Mode
0
1
2
3
SM0
6
SBUF.6
FUNCTION
Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON
SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
Serial Port mode select bit 1. See table below.
Multiple processors communication. Setting this bit to 1 enables the multiproces-
sor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1,
then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if
SM2 = 1, then RI will not be activated if a valid stop bit was not received. In
mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port
runs at a divide by 12 clock of the oscillator. This gives compatibility with the
standard 8052. When set to 1, the serial clock become divide by 4 of the oscilla-
tor clock. This results in faster synchronous serial communication.
Receive enable:
0: Disable serial reception.
1: Enable serial reception.
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared
by software as desired.
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is
the stop bit that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be
cleared only by software.
0
0
1
1
SM1
0
1
0
1
5
SBUF.5
Description
Synchronous
Asynchronous
Asynchronous
Asynchronous
SM1, SM0: Mode Select bits:
W78E054D/W78E052D/W78E051D Data Sheet
4
SBUF.4
- 25 -
Length
3
SBUF.3
11
10
11
8
Publication Release Date: Dec 29, 2009
Baud Rate
Tclk divided by 4 or 12
Variable
Tclk divided by 32 or 64
Variable
2
SBUF.2
1
SBUF.1
Address: 98h
Address: 99h
Revision A09
0
SBUF.0