W78E052DDG Nuvoton Technology Corporation of America, W78E052DDG Datasheet - Page 43

• Manufacturer Part Number: W78E052DDG
• Description: IC MCU 8-BIT 8K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E052DDG

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

W78E054D/W78E052D/W78E051D Data Sheet
11 INSTRUCTION TIMING
A machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts
for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1us if the oscillator fre-
quency is 12MHz.
Each state is divided into a Phase 1 half and a Phase 2 half. The fetch/execute sequences in states
and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed doesn’t require it. If the instruction being exe-
cuted doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the Program
Counter is not incremented. Execution of a one-cycle instruction begins during State 1 of the machine
cycle, when the OPCODE is latched into the Instruction Register. A second fetch occurs during S4 of
the same machine cycle. Execution is complete at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the
second cycle of a MOVX instruction. This is the only time program fetches are skipped. The
fetch/execute sequence for MOVX instructions.
The fetch/execute sequences are the same whether the Program Memory is internal or external to the
chip. Execution times do not depend on whether the Program Memory is internal or external.
the signals and timing involved in program fetches when the Program Memory is external. If Program
Memory is external, then the Program Memory read strobe PSEN is normally activated twice per ma-
chine cycle. If an access to external Data Memory occurs, two PSEN pulse are skipped, because the
address and data bus are being used for the Data Memory access. Note that a Data Memory bus cy-
cle takes twice as much time as a Program Memory bus cycle.
Publication Release Date: Dec 29, 2009
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Revision A09