Z8F082AHH020SG2156 Zilog, Z8F082AHH020SG2156 Datasheet - Page 192

• Manufacturer Part Number: Z8F082AHH020SG2156
• Description: IC ENCORE XP MCU FLASH 8K
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F082AHH020SG2156

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: Q5278375

TCM
Test Complement Under Mask
TCM dst, src
UM012811-0904
Mnemonic
TCM
TCM
TCM
TCM
TCM
TCM
Operation
Description
Flags
Attributes
Escaped Mode Addressing
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. Specify
the bits to be tested by setting a 1 bit in the corresponding bit position in the source oper-
and (the mask). The TCM instruction complements the destination operand and AND’s it
with the source mask (operand). Check the Zero flag to determine the result. If the Z flag
is set, the tested bits were 1. When a TCM operation is completed, the destination and
source operands retain their original values.
Using Escaped Mode Addressing, address modes R or IR specify a Working Register. If
the high nibble of the source or destination address is
inferred. For example, if Working Register R12 (
use ECH as the destination operand in the opcode. To access Registers with addresses
to
C
Z
S
V
D
H
Destination, Source
r1, r2
r1, @r2
R1, R2
R1, @R2
R1, IM
@R1, IM
EFH
, either set the Working Group Pointer, RP[7:4], to
Unaffected.
Set if the result is zero; reset otherwise.
Set if Bit 7 of the result is set; reset otherwise.
Reset to 0.
Unaffected.
Unaffected.
Opcode (Hex)
62
63
64
65
66
67
Operand 1
{r1, r2}
{r1, r2}
R2
R2
R1
R1
CH
) is the desired destination operand,
eZ8 CPU Instruction Set Description
EH
Operand 2
—
—
R1
R1
IM
IM
(1110B), a Working Register is
EH
or use indirect addressing.
Operand 3
—
—
—
—
—
—
User Manual
eZ8 CPU
E0H
182