Z8F0822PJ020EG Zilog, Z8F0822PJ020EG Datasheet - Page 186

• Manufacturer Part Number: Z8F0822PJ020EG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4207; Z8F0822PJ020EG

PS022517-0508
START
Debug Mode
OCD Data Format
The operating characteristics of the Z8 Encore! XP
mode are:
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Entering Debug Mode
The device enters DEBUG mode following any of the following operations:
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Exiting Debug Mode
The device exits DEBUG mode following any of the following operations:
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The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1
Figure
D0
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction.
Match of PC to OCDCNTR register (when enabled)
OCDCNTR register decrements to 0000H (when enabled)
If the
device into DEBUG mode.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-On Reset
Voltage Brownout reset
Asserting the
Driving the
40).
DBG
D1
pin is Low when the device exits Reset, the OCD automatically puts the
DBG
RESET
Figure 40. OCD Data Format
pin Low while the device is in STOP mode initiates a System Reset.
D2
pin Low to initiate a Reset.
D3
D4
®
D5
F0822 Series devices in DEBUG
Z8 Encore! XP
D6
Product Specification
STOP
D7
®
On-Chip Debugger
F0822 Series
bit (see
STOP
173