Z86E7216VSC00TR Zilog, Z86E7216VSC00TR Datasheet
Z86E7216VSC00TR
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... Z86E72/73 OTP Microcontroller Product Specification PS008704-0507 PS008704-0507 Copyright © 2007 by ZiLOG, Inc. All rights reserved. www.zilog.com ...
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... INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. ZiLOG is the registered trademark of ZiLOG, Inc. All other product or service names are the property of their respective owners. PS008704-0507 ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power-On Reset (POR ...
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Features Table 1 lists some of the features of the Z86E72/73 microcontrollers. Table 1. Z86E72/73 Features Part ROM (KB) Z86E73 Z86E72 Note: *General-purpose • Low power consumption—60 mW (typical) • Two standby modes (typical) STOP—2 μA – – HALT—0.8 mA ...
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... The Z86E7X architecture is based on ZiLOG's 8-bit microcontroller core with an Expanded Register File to allow access to register-mapped peripherals, I/O cir- cuits, and powerful counter/timer circuitry. The Z8 offers a flexible I/O scheme, an ...
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SCLK Clock Divider Input Glitch Detect Filter Circuit Figure 1. Z86E7X Counter/Timer Block Diagram Power connections follow the conventions listed in Table 2. Power Connections Connection Power Ground Figure 2 displays the functional block diagram. PS008704-0507 ...
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P00 Port 0 P07 P20 P21 P22 P23 I/O Bit Port 2 P24 Programmable P25 P26 P27 Figure 2. Z86E7X Functional Block Diagram PS008704-0507 Extended Data RAM 512 x 8-Bit Register File E72 Only 256 x 8-Bit Register Bus Internal ...
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Pin Description Figure 3 shows the pin assignments for the standard mode of the 40-pin dual in-line package (DIP). electronically programmable read-only memory (EPROM) mode of the 40-pin DIP. Figure 3. 40-Pin DIP Pin Assignments (Standard Mode) PS008704-0507 Figure 4 ...
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Figure 4. 40-Pin DIP Pin Assignments (EPROM Mode) Figure 5 on page 7 shows the pin assignments for the standard mode of the 44-pin plastic leaded chip carrier (PLCC). assignments for the EPROM mode of the 44-pin PLCC. PS008704-0507 1 ...
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P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 Figure 5. 44-Pin PLCC Pin Assignments (Standard Mode) A9 A10 A11 A12 A13 A14 /PGM A4 Figure 6. 44-Pin PLCC Pin Assignments (EPROM Mode) PS008704-0507 4 ...
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Figure 7 displays the pin assignments for the standard mode of the 44-pin low-profile quad flat pack (LQFP). assignments for the EPROM mode of the 44-pin LQFP. P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 Figure 7. ...
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A9 A10 A11 A12 N/C N/C N/C A13 A14 /PGM A4 Figure 8. 44-Pin LQFP Pin Assignments (EPROM Mode) Table 3 identifies the pins in packages in standard mode. identifies the pins in the 40-pin DIP in EPROM mode. fies ...
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Table 3. Pin Identification (Standard Mode) (Continued) 40-Pin DIP # 44-Pin PLCC # 44-Pin LQFP # Symbol ...
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Table 3. Pin Identification (Standard Mode) (Continued) 40-Pin DIP # 44-Pin PLCC # 44-Pin LQFP # Symbol 23 Table 4. Z86E72/73 40-Pin DIP Identification—EPROM Mode 40-Pin # 1 ...
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Table 4. Z86E72/73 40-Pin DIP Identification—EPROM Mode (Continued) 40-Pin # 34 35–39 40 Table 5. Z86E72/73 44-Pin LQFP/PLCC Pin Identification—EPROM Mode 44-Pin LQFP 44-Pin PLCC 1–2 3–4 5 6–7 8– 15–16 17 18–21 22 23–24 ...
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Table 5. Z86E72/73 44-Pin LQFP/PLCC Pin Identification—EPROM Mode 44-Pin LQFP 44-Pin PLCC 41– Absolute Maximum Ratings Table 6 lists the absolute maximum ratings for the Z86E72/73 microcontrollers. Table 6. Absolute Maximum Ratings Symbol V Supply Voltage (*) MAX ...
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Standard Test Conditions The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 9). From Output Under Test Capacitance Table 7 lists the capacitances ...
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DC Characteristics Table 8 lists the direct current (DC) characteristics. Table 8. DC Characteristics Sym. Parameter Max Input Voltage V Clock Input CH High Voltage V Clock Input CL Low Voltage V Input High Voltage IH V Input Low Voltage ...
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Table 8. DC Characteristics (Continued) Sym. Parameter I Reset Input Current IR I Supply Current CC (WDT off) I Standby Current CC1 (WDT Off) I Standby Current CC2 V Input Common ICR Mode Voltage Range V VCC Low-Voltage LV Detection ...
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Table 8. DC Characteristics (Continued) Sym. Parameter V Static RAM Data RAM Retention Voltage Notes: ICC1 Crystal/Resonator External Clock Drive 1. All outputs unloaded, inputs at rail 2. CL1 = CL2 = 100 pF 3. Same as note [4] except ...
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AC Characteristics Figure 10 shows the external input/output (I/O) or memory read and write timing. Table 9 describes the I/O or memory read and write timing. R//W 12 Port 0, /DM 18 Port 1 1 /AS 4 /DS (Read) Port ...
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Table 9. External I/O or Memory Read and Write Timing No. Symbol Parameter 1 TdA(AS) Address Valid to /AS Rising Delay 2 TdAS(A) /AS Rising to Address Float Delay 3 TdAS(DR) /AS Rising to Read Data Required Valid 4 TwAS ...
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Table 9. External I/O or Memory Read and Write Timing (Continued) No. Symbol Parameter 17 TdAS(DS) /AS Rising to /DS Falling Delay 18 TdDM(AS) /DM Valid to /AS Falling Delay 19 TdDS(DM) /DS Rise to /DM Valid Delay 20 ThDS(A) ...
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Clock T IN IRQ N Clock Setup Stop Mode Recovery Source Table 10. Additional Timing No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input ...
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Table 10. Additional Timing (Continued) No Symbol Parameter 6 TpTi Timer Input Period 7 TrTin,TfTi Timer Input Rise and Fall Timers 8A TwIL Interrupt Request Low Time 8B TwIL Int. Request Low Time 9 TwIH Interrupt Request Input High Time ...
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Data In Valid Data (Input) RDY (Output) Data Out 7 DAV (Output) RDY (Input) Figure 13. Output Handshake Timing PS008704-0507 2 3 Delayed DAV 4 Figure 12. Input Handshake Timing Data Out Valid ...
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Table 11. Handshake Timing No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) Data In Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) DAV Falling to RDY Falling Delay 5 TdDAVId(RDY) DAV Rising to RDY Falling Delay ...
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Pin Functions /DS (Output, Active Low) Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available before the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that ...
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I/O direction to Port 0 of the upper nibble P07–P04. The lower nib- ble must have the same direction as the upper nibble. For external memory references, Port 0 can provide address bits A11–A8 (lower nibble) or ...
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Z86E7X MCU OEN Out In In Trip Point Buffer PS008704-0507 4 Port 0 (I/O or A15–A8) 4 Optional Handshake Controls /DAV0 and RDY0 (P32 and P35) * Note: On P00 and P07 only 0.4 VDD ** POIM, DI, DO Mask ...
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... Port 1 (P17–P10) Port multiplexed Address (A7–A0) and Data (D7–D0), CMOS-compatible port. Port 1 is dedicated to the ZiLOG ZBus operations of Port 1 are supported by the Address Strobe (/AS) and Data Strobe (/DS) lines and by the Read/Write (R//W) and Data Memory (/DM) control lines. Data memory read/write operations are done through this port. If more than 256 external locations are required, Port 0 outputs the additional lines ...
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Z86E7X MCU OEN Out In PS008704-0507 Port 1 8 (I/O or AD7 - AD0) Optional Handshake Controls /DAV1 and RDY1 (P33 and P34) R 500 K OTP Microcontroller 29 PAD Auto Latch ...
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Port 2 (P27–P20) Port 8-bit, bidirectional, CMOS-compatible I/O port (see eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A software option is avail- ...
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The CCP wakes up with the 8 bits of Port 2 configured as inputs with open-drain outputs. Port 2 also has an 8-bit input OR and an AND gate that can be used to wake up the part. P20 can ...
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Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge-triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer ...
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P31 (AN1) PREF1 P32 (AN2) P33 (REF2) From Stop-Mode Recovery Source Comparator Outputs These outputs can be programmed to be output on P34 and P37 through the PCON register PS008704-0507 Pref1 P31 P32 Z86E7X P33 MCU Port 3 (I/O or ...
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CTR0, D0 Out 34 T8_Out CTR2, D0 Out 35 T16_Out CTR1, D6 Out 36 T8/16_Out PS008704-0507 VDD MUX Pad P34 VDD MUX Pad P35 VDD MUX Pad P36 Figure 19. Port 3 Configuration OTP Microcontroller 34 ...
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Active Low) Reset initializes the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer, Stop-Mode Recovery, Low-Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin Low for ...
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Functional Description The Z86E72/73 microcontrollers incorporate special functions to enhance the Z8's functionality in consumer and battery-operated applications. Reset The device is reset in one of the following conditions: • Power-On Reset • Watch-Dog Timer • Stop-Mode Recovery Source • ...
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Location of First Byte of Instruction Executed 12 After RESET 11 10 Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) RAM The Z86E72 has a 768-byte RAM; 256 bytes make up the register file. The remaining 512 bytes ...
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Note: The Extended Data RAM cannot be used as STACK or instruction/code memory. Accessing the Extended Data RAM has the following condition: P01M register bits D4–D3 cannot be set to 11. External Memory The Z86E72/73 microcontrollers address ...
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Not Addressable 0 Expanded Register File The register file has been expanded to allow for additional system control regis- ters and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 ...
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The upper nibble of the register pointer working register group of 16 bytes in the register file, out of the possible 256, is accessed. The lower nibble selects the expanded register file bank and, in the case of the Z86E7X ...
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REGISTER POINTER Working Register Expanded Register Group Pointer Bank Group Pointer Z8 Register File (Bank 0)** EXPANDED REG. GROUP (0) REGISTER** RESET CONDITION ( ...
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Figure 22. Expanded Register File Architecture R253 Default setting after reset = 0000 0000 Register File The register file (bank 0) consists of 4 I/O port registers, 236 general-purpose reg- isters, and ...
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The upper nibble of the register file address provided by the register pointer specifies the active working-register group Stack The Z86E7X external data memory or the internal ...
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Table 13. Expanded Register Group D (Continued) (D) 09h (D) 08h (D) 07h (D) 06h (D) 05h (D) 04h (D) 03h (D) 02h (D) 01h (D) 00h HI8(D)0Bh Register This register (Table Counter/Timer0. This register is typically used to hold ...
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HI16(D)09h Register This register (Table Counter/Timer16. This register holds the MS-Byte of the data. Table 16. HI16(D)09h Register Field T16_Capture_HI 76543210 L016(D)08h Register This register (Table Counter/Timer16. This register holds the LS-Byte of the data. Table 17. LO16(D)08h Register Field ...
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TC8H(D)05h Register Table 20 describes the Counter/Timer8 High Hold Register. Table 20. TC8H(D)05h Register Field T8_Level_HI TC8L(D)04h Register Table 21 describes the Counter/Timer8 Low Hold Register. Table 21. TC8L(D)04h Register Field T8_Level_LO CTR0(D)00h Register Table 22 describes the Counter/Timer8 Control ...
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Table 22. CTR0(D)00h Register (Continued) Field Counter_INT_Mask P34_Out Note: *Indicates the value upon Power-On Reset T8 Enable This field enables T8 when set (written Single/Modulo-N When set to 0 (modulo-n), the counter reloads the initial value when the ...
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Counter_INT_Mask Set this bit to allow interrupt when T8 has a time out. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. CTR1(D)01h Register This register (Table Table 23. CTR1(D)01h Register Field ...
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Table 23. CTR1(D)01h Register (Continued) Field Initial_T8_Out/Rising_Edge Initial_T16_Out/Falling _Edge Note: * Indicates the value upon Power-On Reset. Mode the counter/timers are in the transmit mode; otherwise, they are in the demodulation mode. P36_Out/Demodulator_Input In transmit mode, ...
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Operation Mode” terminates the “Ping-Pong Mode” operation. When set to 10, T16 is immediately forced When set to 11, T16 is immediately forced demodulation mode, this field defines the width of the glitch ...
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CTR2(D)02h Register Table 24 describes the Counter/Timer16 Control Register. Table 24. CTR2(D)02h Register Field T16_Enable Submode/Modulo-N Time_Out T16 _Clock Capture_INT_Mask Counter_INT_Mask P35_Out Note: * Indicates the value upon Power-On Reset. T16_Enable This field enables T16 when set to 1. Single/Modulo-N ...
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In demodulation mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge, but ignores the subsequent edges. For details, see “T16 Demodulation Mode” ...
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Counter/Timer Functional Blocks The following are the counter/timer functional blocks: • Input circuit • Eight-bit counter/timer circuits (page 54) • Sixteen-bit counter/timer circuits (page 59) • Output circuit (page 62) Input Circuit The edge detector monitors the input signal on ...
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Eight-Bit Counter/Timer Circuits Figure 26 shows the 8-bit counter/timer circuits. Z8 Data Bus Pos Edge Neg Edge CTR0 D4, D3 Clock SCLK Select Z8 Data Bus Figure 26. Eight-Bit Counter/Timer Circuits T8 Transmit Mode When T8 is enabled, the output ...
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Reset T8_Enable Bit Set Time-out Status Bit (CTR0, D5) and generate Timeout_Int if enabled Figure 27. Transmit Mode Flowchart PS008704-0507 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, D7 Yes LOW T8_OUT Value Load TC8L Reset T8_OUT Enable T8 ...
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Enable” Command, T8_OUT Switches To Its Initial Value (CTR1 D1) Figure 28. T8_OUT in Single-Pass Mode T8_OUT TC8L “Counter Enable” Command, T8_OUT Switches To Its Initial Value (CTR1 D1) Figure 29. T8_OUT in Modulo-N Mode You can modify the ...
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T8 Demodulation Mode You need to program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge ...
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Figure 30. Demodulation Mode Count Capture Flowchart Disable T8 Figure 31. Demodulation Mode Flowchart PS008704-0507 T8 (8-Bit) Demodulation Mode No T8 Enable CTR0, D7 Yes FFh → TC8 No First Edge Present Yes Enable TC8 No T8_Enable Bit Set Yes ...
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Sixteen-Bit Counter/Timer Circuits Figure 32 shows the 16-bit counter/timer circuits. Z8 Data Bus Pos Edge Neg Edge CTR2 D4, D3 Clock SCLK Select Z8 Data Bus Figure 32. Sixteen-Bit Counter/Timer Circuits T16 Transmit Mode In Normal or Ping-Pong Mode, the ...
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Enable” Command, T16_OUT Switches To Its Initial Value (CTR1 D0) Figure 33. T16_OUT in Single-Pass Mode TC16H*256+TC16L T16_OUT “Counter Enable” Command, T16_OUT Switches To Its Initial Value (CTR1 D0) Figure 34. T16_OUT in Modulo-N Mode You can modify the ...
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CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A time out of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In ...
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Starting Ping-Pong Mode First, make sure both counter/timers are not running. Then set T8 into Single- Pass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set Ping- Pong Mode (CTR1 D2, D3). These instructions do not have ...
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Interrupt Request Table 26. Interrupt Types, Sources, and Vectors Name Source IRQ0 /DAV0, IRQ0 IRQ1 IRQ1 IRQ2 /DAV2, IRQ2, T IRQ3 T16 IRQ4 T8 PS008704-0507 IRQ0 IRQ IRQ IMR IPR Global Interrupt Enable Priority Logic Vector Select ...
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When more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. This disables all subsequent interrupts, saves ...
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The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with ...
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HALT HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt ...
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Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port this location brings the compar- ator outputs to P34 and P37, and a 0 releases the port to its standard I/O configu- ration. ...
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VCC P31 P32 P33 To IRQ1 P27 P20 P23 P20 P27 Figure 40. Stop-Mode Recovery Register PS008704-0507 SMR SMR SMR ...
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SCLK/TCLK Divide-by-16 Select (D0 the SMR controls a Divide-by-16 prescaler of SCLK/TCLK purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK sources interrupt logic). After ...
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Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the “fast” wake up is selected, the Stop- Mode Recovery source needs to ...
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Stop-Mode Recovery Register 2 (SMR2) This register (see SMR2. SMR2 (0F Default setting after reset Note: If used in conjunction with SMR, either of the two specified events causes a ...
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Watch-Dog Timer Mode Register (WDTMR) The WDT is a retriggerable one-shot timer that resets the reaches its termi- nal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on subsequent executions of ...
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WDT Time Select (D0, D1) This bit selects the WDT time period configured as shown in Table 29. WDT Time Select Notes: TpC = XTAL clock cycle The default on reset is 10 ...
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Clock Filter CK Source Select (WDTMR) XTAL INTERNAL RC OSC. Low Operating Voltage Det. + VDD - VBO/VLV 2V REF . WDT From Stop Mode 12 ns Glitch Filter Recovery Source Stop Delay Select (SMR) * /CLR1 and ...
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Software-Selectable Options There are four Software-Selectable Options to choose from based on the ROM- based parts mask options. Register (F0) EH OTP byte is where these options are controlled. These options are listed in Table 30. Software-Selectable Options Bit Name ...
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EPROM Programming Table 31 describes the programming and test modes. Table 31. Programming and Test Modes User/Test Mode Device Pin # P33 P32 User Modes V EPM PP EPROM Read Program Program ...
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Table 32 lists the timing of the programming waveform. Table 32. Timing of Programming Waveform Parameters Figure 45 shows the EPROM read timing diagram. the ...
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PS008704-0507 Figure 45. EPROM Read OTP Microcontroller 78 ...
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V IH Address Data EPM /PGM ...
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Figure 47. Programming EPROM, RAM Protect, and 16K Size Selection Figure 48 shows the programming flowchart. PS008704-0507 OTP Microcontroller 80 ...
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PS008704-0507 Figure 48. Programming Flowchart OTP Microcontroller 81 ...
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Expanded Register File Control Registers (0D) Figure 49 through (0D). CTR0 (0D Default setting after reset Figure 49. TC8 Control Register—(0D) 0H: Read/Write Except Where Noted PS008704-0507 Figure 51 show ...
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CTR1 (0D Default setting after reset Figure 50. T8 and T16 Common Control Functions—(0D) 1H: Read/Write PS008704-0507 Transmit Mode R/W 0 T16_OUT is 0 initially 1 T16_OUT is 1 initially ...
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CTR2 (0D) 02H Default setting after reset Figure 51. T16 Control Register—(0D) 2H: Read/Write Except Where Noted PS008704-0507 OTP Microcontroller 0 = P35 is Port Output * 1 = P35 is ...
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Expanded Register File Control Registers (0F) Figure 52 through SMR (0F Default setting after reset ** Default setting after reset and Stop-Mode Recovery Figure 52. Stop-Mode Recovery Register—(F) 0BH: D6–D0=Write ...
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SMR2 (0F Default setting after reset Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. Figure 53. Stop-Mode Recovery Register 2—(0F) DH: ...
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OPT (0F WDTMR (0F Default setting after reset Figure 55. Watch-Dog Timer Mode Register—(F) 0FH: Write Only PS008704-0507 Port 0 (0–3) ...
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PCON (0F *Default setting after reset Figure 56. Port Configuration Register (PCON)—(0F) 0H: Write Only R246 P2M *Default setting after reset Figure 57. ...
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Z8 Standard Control Register Diagrams Figure 58 through R247 P3M Default setting after reset Figure 58. Port 3 Mode Register—F7H: Write Only PS008704-0507 Figure 66 show the Z8 standard control register ...
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Figure 59. Port 0 and 1 Mode Register—F8H: Write Only R249 IPR PS008704-0507 OTP Microcontroller P00–P03 Mode 00 Output 01 Input* 1X A11–A8 Stack ...
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Figure 60. Interrupt Priority Registers—(0) F9H: Write Only R250 IRQ Default setting after reset = 0000 0000 Figure 61. Interrupt Request Register—(0) FAH: Read/Write R251 IMR ...
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R252 Flags Figure 63. Flag Register—(0) FCH: Read/Write R253 Default Setting After Reset = 0000 Figure 64. Register Pointer—(0) FDH: Read/Write R254 SPH ...
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Figure 66. Stack Pointer Low—(0) FFH: Read/Write PS008704-0507 OTP Microcontroller 93 ...
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Package Information The Z86E72/73 is available in 40-pin DIP page 95), and 44-pin PLCC Figure 67. 40-Pin DIP Package Diagram PS008704-0507 (Figure 67), 44-pin LQFP (Figure 69 on page 96) packages. OTP Microcontroller 94 (Figure 68 on ...
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0-7° Figure 68. 44-Pin LQFP Package Diagram PS008704-0507 DETAIL OTP Microcontroller 95 ...
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Figure 69. 44-Pin PLCC Package Diagram PS008704-0507 OTP Microcontroller 96 ...
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... Figure 70 shows an example of what the ordering codes represent. Example: Z 86E73 16 P Figure 70. Ordering Codes Example For fast results, contact your local ZiLOG sales office for assistance in ordering the part wanted. Package P = Plastic DIP A = Low-profile Quad Flat Pack V = Plastic Chip Carrier Temperature ° ...
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... Customer Support For answers to technical questions about the product, documentation, or any other issues with ZiLOG’s offerings, please visit ZiLOG’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit ZiLOG’s Technical Support at http://support.zilog.com. ...