Z86E7216VSC00TR Zilog, Z86E7216VSC00TR Datasheet - Page 54

IC MCU OTP 16K ZIRC 44PLCC

Z86E7216VSC00TR

Manufacturer Part Number
Z86E7216VSC00TR
Description
IC MCU OTP 16K ZIRC 44PLCC
Manufacturer
Zilog
Series
Z8®r
Datasheet

Specifications of Z86E7216VSC00TR

Core Processor
Z8
Core Size
8-Bit
Speed
16MHz
Peripherals
LVD, POR, WDT
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
748 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z86E7216VSC00TR
Manufacturer:
Zilog
Quantity:
10 000
PS008704-0507
Note:
Operation Mode” terminates the “Ping-Pong Mode” operation. When set to 10,
T16 is immediately forced to a 0. When set to 11, T16 is immediately forced to a 1.
In demodulation mode, this field defines the width of the glitch that must be filtered
out.
Initial_T8_Out/Rising_Edge
In transmit mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the
output of T8 is set to 1 when it starts to count. When this bit is set to 1 or 0,
T8_OUT is set to the opposite state of this bit. This ensures that when the clock is
enabled, a transition occurs to the initial state set by CTR1, D1.
In demodulation mode, this bit is set to 1 when a rising edge is detected in the
input signal. To reset it, a 1 must be written to this location.
Initial_T16 Out/Falling _Edge
In transmit mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it
is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in
Normal or Ping-Pong Mode (CTR1, D3, D2). When this bit is set, T16_OUT is set
to the opposite state of this bit. This ensures that when the clock is enabled a tran-
sition occurs to the initial state set by CTR1, D0.
In demodulation mode, this bit is set to 1 when a falling edge is detected in the
input signal. To reset it, a 1 must be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled
causes unpredictable output from T8/T16 out.
OTP Microcontroller
50

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