ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 37

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F276Z5
4.4.12
Table 18.
XFlash interface control register
This register is used to configure the XFLASH interface behavior on the XBUS. It allows to
set the number of wait states introduced on the XBUS before the internal READY signal is
given to the ST10 bus master.
XFICR (0xE E000h)
Table 19.
15
WS(3:0)
SEQER
RESER
WPF
Bit
Bit
14
Flash error register (continued)
XFlash interface control register
13
Sequence error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L,
FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. in this
case no write operation is executed. This bit has to be software reset.
Resume error
This bit is automatically set when a suspended program or erase operation is not
resumed correctly due to a protocol error. In this case the suspended operation is
aborted. This bit has to be software reset.
Write protection flag
This bit is automatically set when trying to program or erase in a sector write
protected. In case of multiple sector erase, the not protected sectors are erased, while
the protected sectors are not erased and bit WPF is set. This bit has to be software
reset.
Wait state setting
These three bits are the binary coding of the number of wait states introduced by the
XFLASH interface through the XBUS internal READY signal. Default value after reset
is 1111, that is the up to 15 wait states are set. The following recommendations for the
ST10F276Z5 are hereafter reported:
For f
For f
CPU
CPU
12
> 40 MHz1 Wait-StateWS(3:0) = ‘0001’
≤ 40 MHz0 Wait-StateWS(3:0) = ‘0000’
11
10
reserved
9
XBUS
8
Function
7
Function
6
5
4
Internal Flash memory
WS3
RW
3
Reset value: 000Fh
WS2
RW
2
WS1
RW
1
37/239
WS0
RW
0