MC9S08QG84CFQE Freescale Semiconductor, MC9S08QG84CFQE Datasheet - Page 69

• Manufacturer Part Number: MC9S08QG84CFQE
• Description: IC MCU 8BIT B54 RATING 8-DFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG84CFQE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1
5.8.1
This direct page register includes status and control bits, which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
Freescale Semiconductor
Bit 5 is a reserved bit that must always be written to 0.
IRQMOD
IRQPDD
IRQACK
Reset
IRQPE
IRQIE
Field
IRQF
6
4
3
2
1
0
W
R
Interrupt Pin Request Status and Control Register (IRQSC)
Interrupt Request (IRQ) Pull Device Disable — This read/write control bit is used to disable the internal pullup
device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. See
0 IRQ event on falling edges only.
1 IRQ event on falling edges and low levels.
0
0
7
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
= Unimplemented or Reserved
IRQPDD
Section 5.5.2.2, “Edge and Level
0
6
Table 5-3. IRQSC Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
5
0
0
1
IRQPE
0
4
Sensitivity,” for more details.
Description
Chapter 5 Resets, Interrupts, and General System Control
IRQF
3
0
IRQACK
0
0
2
IRQIE
0
1
IRQMOD
0
0
67