C8051F305-GMR Silicon Laboratories Inc, C8051F305-GMR Datasheet - Page 125

IC 8051 MCU 2K FLASH 11QFN

C8051F305-GMR

Manufacturer Part Number
C8051F305-GMR
Description
IC 8051 MCU 2K FLASH 11QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets

Specifications of C8051F305-GMR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
For Use With
336-1444 - ADAPTER PROGRAM TOOLSTICK F300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F305-GMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F305-GMR
Quantity:
1 061
13.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver; see
this procedure. Figure 13.7 shows a typical Slave Receiver sequence. Two received data bytes are shown,
though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur
before the ACK cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 13.7. Typical Slave Receiver Sequence
SLA
Interrupt
W
A
Data Byte
Rev. 2.9
Interrupt
A
S = START
P = STOP
A = ACK
R = READ
SLA = Slave Address
Data Byte
C8051F300/1/2/3/4/5
Interrupt
A
Section 13.5.4
Interrupt
P
for details on
125

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