MC9S08QG8CFFE Freescale Semiconductor, MC9S08QG8CFFE Datasheet - Page 152

• Manufacturer Part Number: MC9S08QG8CFFE
• Description: IC MCU 8K FLASH 10MHZ 16-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8CFFE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Internal Clock Source (S08ICSV1)
10.4
10.4.1
The states of the ICS are shown as a state diagram and are described in the following sections. The arrows
indicate the allowed movements between the states.
10.4.1.1
FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when all the
following conditions occur:
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
150
FLL Bypassed
External Low
Power(FBELP)
•
•
•
IREFS=0
CLKS=10
BDM Disabled
and LP=1
CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz.
Functional Description
Operational Modes
FLL Engaged Internal (FEI)
Entered from any state
when MCU enters stop
IREFS=0
CLKS=10-
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 10-7. Clock Switching Modes
FLL Engaged
External (FEE)
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=00
IREFS=0
CLKS=00
Stop
FLL Bypassed
Internal (FBI)
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
IREFS=1
CLKS=01
BDM Enabled
or LP=0
Freescale Semiconductor
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1