MC9S08AC16MFGE Freescale Semiconductor, MC9S08AC16MFGE Datasheet - Page 106

• Manufacturer Part Number: MC9S08AC16MFGE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16MFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: RS- 232/SCI/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: HCS08
• No. Of I/o's: 34
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output
106
PTGDS[6:0]
PTGSE[6:0]
Reset
Reset
Field
Field
6:0
6:0
W
W
R
R
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high
output drive for the associated PTG pin.
0 Low output drive enabled for port G bit n.
1 High output drive enabled for port G bit n.
0
0
0
0
7
7
Figure 6-43. Output Slew Rate Control Enable for Port G Bits (PTGSE)
Figure 6-44. Output Drive Strength Selection for Port G (PTGDS)
PTGSE6
PTGDS6
0
0
6
6
Table 6-34. PTGSE Register Field Descriptions
Table 6-35. PTGDS Register Field Descriptions
PTGSE5
PTGDS5
MC9S08AC16 Series Data Sheet, Rev. 8
0
0
5
5
PTGSE4
PTGDS4
0
0
4
4
Description
Description
PTGDS3
PTGSE3
3
0
3
0
PTGDS2
PTGSE2
0
0
2
2
PTGDS1
PTGSE1
Freescale Semiconductor
0
0
1
1
PTGSE0
PTGDS0
0
0
0
0