MC9S08AC16MFDE Freescale Semiconductor, MC9S08AC16MFDE Datasheet - Page 228

• Manufacturer Part Number: MC9S08AC16MFDE
• Description: IC MCU 8BIT 16K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16MFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 48QFN EP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (S08IICV2)
13.2
This section describes each user-accessible pin signal.
13.2.1
The bidirectional SCL is the serial clock line of the IIC system.
13.2.2
The bidirectional SDA is the serial data line of the IIC system.
13.3
This section consists of the IIC register descriptions in address order.
Refer to the direct-page register summary in the
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
228
External Signal Description
Register Definition
SCL — Serial Clock Line
SDA — Serial Data Line
CTRL_REG
ADDR_DECODE
Control
Address
Clock
Input
Sync
Figure 13-2. IIC Functional Block Diagram
FREQ_REG
MC9S08AC16 Series Data Sheet, Rev. 8
SCL
Arbitration
ADDR_REG
Control
memory
Start
Stop
SDA
chapter of this document for the absolute address
STATUS_REG
Interrupt
Compare
Register
Address
In/Out
Data
Shift
DATA_MUX
DATA_REG
Data Bus
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