C8051F523A-IM Silicon Laboratories Inc, C8051F523A-IM Datasheet - Page 111

• Manufacturer Part Number: C8051F523A-IM
• Description: IC 8051 MCU 4K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F523A-IM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1491-5

SFR Definition 11.2. RSTSRC: Reset Source
Note: Software should avoid read modify write instructions when writing values to RSTSRC.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
—
UNUSED. Read = 1, Write = don't care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0.
1: Read: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit.
1: Read: Source of last reset was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout.
1: Read: Source of last reset was a Missing Clock Detector timeout.
detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing 1 to this bit before the V
and stabilized may cause a system reset. See register VDDMON (SFR Definition 11.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
nate.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
FERROR C0RSEF
Write: Comparator0 is not a reset source.
Write: Comparator0 is a reset source (active-low).
Write: No Effect.
Write: Forces a system reset.
Write: Missing Clock Detector disabled.
Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
Write: V
Write: V
Bit6
R
DD
DD
monitor is not a reset source.
monitor is a reset source.
R/W
Bit5
SWRSF
R/W
C8051F52x/F52xA/F53x/F53xA
Bit4
WDTRSF MCDRSF
Rev. 1.3
Bit3
R
DD
monitor reset; all other reset flags indetermi-
DD
monitor reset.
R/W
Bit2
PORSF
R/W
Bit1
DD
SFR Address:
monitor is enabled
PINRSF
Bit0
R
Reset Value
Variable
0xEF
DD
111