MCR908JL3ECFAE Freescale Semiconductor, MCR908JL3ECFAE Datasheet - Page 61

• Manufacturer Part Number: MCR908JL3ECFAE
• Description: IC MCU 4K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JL3ECFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

5.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
5.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run.
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option
register is zero, then the computer operating properly module (COP) is enabled and remains active in wait
mode.
Figure 5-16
Freescale Semiconductor
and
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
Figure 5-17
R/W
IAB
IDB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
IAB
IDB
WAIT ADDR
last instruction.
Figure 5-16. Wait Recovery from Interrupt or Break
$A6
show the timing for WAIT recovery.
PREVIOUS DATA
$6E0B
Figure 5-15. Wait Mode Entry Timing
$A6
RST
MC68HC908JL3E Family Data Sheet, Rev. 4
pin OR CPU interrupt OR break interrupt
WAIT ADDR + 1
$A6
$6E0C
NEXT OPCODE
$01
$00FF
$0B
SAME
$00FE
$6E
SAME
$00FD
SAME
SAME
$00FC
Figure 5-15
Low-Power Modes
shows
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